Nanditha P. Rao

According to our database, Nanditha P. Rao authored at least 15 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping.

Shubhayu Das, Nanditha P. Rao, Sharad Sinha

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

2023

MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA.

Shivani Shah, Nanditha P. Rao

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Cacheaccel_Simulator.

Shivani Shah, Nanditha P. Rao

Dataset, February, 2022

FastMem: A Fast Architecture-aware Memory Layout Design.

Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs.

Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An FPGA based Tiled Systolic Array Generator to Accelerate CNNs.

Veerendra S. Devaraddi, Nanditha P. Rao

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

Variable Bit-Precision Vector Extension for RISC-V Based Processors.

Risikesh RK, Sharad Sinha, Nanditha P. Rao

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

FPGA Accelerated Parameterized Cache Simulator.

Shivani Shah, Sahithi Meenakshi Vutakuru, Nanditha P. Rao

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design.

Prashant Mata, Nanditha P. Rao

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher.

Shivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2018

Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology.

Nanditha P. Rao, Madhav P. Desai

Microelectron. J., 2018

2017

Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs.

Nanditha P. Rao, Madhav P. Desai

CoRR, 2017

2016

Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates.

Nanditha P. Rao, Madhav P. Desai

CoRR, 2016

2015

A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients.

Nanditha P. Rao, Madhav P. Desai

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

On the likelihood of multiple bit upsets in logic circuits.

Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai

CoRR, 2014