Nan Xing
Orcid: 0000-0002-4178-4302
According to our database1,
Nan Xing
authored at least 23 papers
between 2008 and 2024.
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Bibliography
2024
Investigating the anti-lung cancer properties of Zhuang medicine Cycas revoluta Thunb. leaves targeting ion channels and transporters through a comprehensive strategy.
Comput. Biol. Chem., 2024
2023
Remote. Sens., March, 2023
Expert Syst. Appl., 2023
2022
Remote. Sens., 2022
2021
2020
Highest Maximum Power Point of Radially Distant Inductively Coupled Power Receivers With Deep Submicron CMOS.
IEEE Trans. Ind. Informatics, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the ICAIP 2020: 4th International Conference on Advances in Image Processing, 2020
2019
180-nm 85%-Efficient Inductively Coupled Switched Resonant Half-Bridge Power Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
2017
Multim. Tools Appl., 2017
Power analysis and maximum output-power scheme for inductively coupled resonant power receivers.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Proceedings of the 25th IEEE International Symposium on Industrial Electronics, 2016
Adaptive feature extraction based on Stacked Denoising Auto-encoders for asynchronous motor fault diagnosis.
Proceedings of the 9th International Congress on Image and Signal Processing, 2016
2013
A 0.026mm<sup>2</sup> 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line.
Proceedings of the ESSCIRC 2013, 2013
2012
A 0.004mm<sup>2</sup> 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm<sup>2</sup> 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
2010
A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
A high resolution capacitance deviation-to-digital converter utilizing time stretching.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
2008
Proceedings of the Twenty-First International Florida Artificial Intelligence Research Society Conference, 2008