Nan Wang

According to our database, Nan Wang authored at least 23 papers between 2013 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

M-CBN: Manifold constrained joint image dehazing and super-resolution based on chord boosting network.

Pengyu Wang, Hongqing Zhu, Han Zhang, Nan Wang

Pattern Recognit., 2023

2022

TMS-GAN: A Twofold Multi-Scale Generative Adversarial Network for Single Image Dehazing.

Pengyu Wang, Hongqing Zhu, Hui Huang, Han Zhang, Nan Wang

IEEE Trans. Circuits Syst. Video Technol., 2022

2020

SS3: Security-Aware Vendor-Constrained Task Scheduling for Heterogeneous Multiprocessor System-on-Chips.

Manting Yao, Weina Yuan, Nan Wang, Zeyu Zhang, Yuan Qiu, Yichuan Liu

Proceedings of the IEEE International Conference on Networking, Sensing and Control, 2020

2019

Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis.

Nan Wang, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu

Integr., 2019

Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems.

Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen

Integr., 2019

2018

Weighted Domain Transfer Extreme Learning Machine and Its Online Version for Gas Sensor Drift Compensation in E-Nose Systems.

Zhiyuan Ma, Guangchun Luo, Ke Qin, Nan Wang, Weina Niu

Wirel. Commun. Mob. Comput., 2018

Online Sensor Drift Compensation for E-Nose Systems Using Domain Adaptation and Extreme Learning Machine.

Zhiyuan Ma, Guangchun Luo, Ke Qin, Nan Wang, Weina Niu

Sensors, 2018

Power-gating-aware scheduling with effective hardware resources optimization.

Nan Wang, Wei Zhong, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu

Integr., 2018

Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis.

Nan Wang, Song Chen, Jianmo Ni, Xiaofeng Ling, Yu Zhu

IEEE Access, 2018

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints.

Nan Wang, Manting Yao, Dongxu Jiang, Song Chen, Yu Zhu

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Flexible Broadband Single RF Architecture Based on Time-Modulated Array.

Xiaofeng Ling, Nan Wang

Proceedings of the Communications, Signal Processing, and Systems, 2018

2017

Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis.

Cong Hao, Jianmo Ni, Nan Wang, Takeshi Yoshimura

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Unified Scheduling Approach for Power and Resource Optimization With Multiple V_dd or/and V_th in High-Level Synthesis.

Cong Hao, Nan Wang, Takeshi Yoshimura

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016

Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design.

Nan Wang, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Tabu search based multiple voltage scheduling under both timing and resource constraints.

Jianmo Ni, Nan Wang, Takeshi Yoshimura

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Primal-dual method based simultaneous functional unit and register binding.

Jianmo Ni, Cong Hao, Nan Wang, Qian Ai, Takeshi Yoshimura

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis.

Nan Wang, Song Chen, Wei Zhong, Nan Liu, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Leakage Power Aware Scheduling in High-Level Synthesis.

Nan Wang, Song Chen, Cong Hao, Haoran Zhang, Takeshi Yoshimura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013

Min-cut based leakage power aware scheduling in high-level synthesis.

Nan Wang, Song Chen, Takeshi Yoshimura

Proceedings of the International Symposium on Quality Electronic Design, 2013

Mobility overlap-removal based leakage power aware scheduling in high-level synthesis.

Nan Wang, Song Chen, Yuhuan Sun, Takeshi Yoshimura

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Power and resource aware scheduling with multiple voltages.

Haoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Timing and resource constrained leakage power aware scheduling in high-level synthesis.

Nan Wang, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Interconnection allocation between functional units and registers in High-Level Synthesis.

Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu

Proceedings of the IEEE 10th International Conference on ASIC, 2013