Nan-Chi Chou
According to our database1,
Nan-Chi Chou
authored at least 18 papers
between 1992 and 2011.
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Bibliography
2011
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
2009
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
Proceedings of the 46th Design Automation Conference, 2009
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
2005
Proceedings of the 2005 International Symposium on Physical Design, 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
A practical cut-based physical retiming algorithm for field programmable gate arrays.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
2003
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages.
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
Proceedings of the 40th Design Automation Conference, 2003
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
An optimal probe testing algorithm for the connectivity verification of MCM substrates.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992