Nan-Cheng Lai

According to our database, Nan-Cheng Lai authored at least 5 papers between 2004 and 2013.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2013

Delay Test with Embedded Test Pattern Generator.

Nan-Cheng Lai, Sying-Jyan Wang

J. Inf. Sci. Eng., 2013

2008

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests.

Nan-Cheng Lai, Sying-Jyan Wang

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs.

Nan-Cheng Lai, Sying-Jyan Wang

Proceedings of the 16th Asian Test Symposium, 2007

2006

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.

Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2004

Low Power BIST with Smoother and Scan-Chain Reorder .

Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004