Namhyung Kim
Orcid: 0000-0002-2030-6010
According to our database1,
Namhyung Kim
authored at least 10 papers
between 2014 and 2023.
Collaborative distances:
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Bibliography
2023
SGCN: Exploiting Compressed-Sparse Features in Deep Graph Convolutional Network Accelerators.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
ComPreEND: Computation Pruning through Predictive Early Negative Detection for ReLU in a Deep Neural Network Accelerator.
IEEE Trans. Computers, 2022
Slice-and-Forge: Making Better Use of Caches for Graph Convolutional Network Accelerators.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
2021
Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing.
IEEE Comput. Archit. Lett., 2021
2020
NVDIMM-C: A Byte-Addressable Non-Volatile Memory Module for Compatibility with Standard DDR Memory Interfaces.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems.
ACM Trans. Archit. Code Optim., 2018
2016
J. Syst. Archit., 2016
2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
2014
A Triple-Push Voltage Controlled Oscillator in 0.13-µm RFCMOS Technology Operating Near 177GHz.
IEICE Trans. Electron., 2014