Nam Ho

According to our database, Nam Ho authored at least 18 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation.

Fabian Schätzle, Carlos Falquez, Stefan Heinen, Nam Ho, Antoni Portero, Estela Suarez, Johannes Van Den Boom, Stefan van Waasen

Proceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design, 2024

Data Prefetching on Processors with Heterogeneous Memory.

Berk Saglam, Nam Ho, Carlos Falquez, Antoni Portero, Fabian Schätzle, Estela Suarez, Dirk Pleiter

Proceedings of the International Symposium on Memory Systems, 2024

Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC.

Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Carlos Falquez, Antoni Portero, Nam Ho, Estela Suarez, Polydoros Petrakis, Manolis Marazakis, Francesco Sgherzi, Ivan Fernandez, Romain Dolbeau, Dirk Pleiter

Proceedings of the Architecture of Computing Systems - 37th International Conference, 2024

2023

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores.

Antoni Portero, Carlos Falquez, Nam Ho, Polydoros Petrakis, Stepan Nassyr, Manolis Marazakis, Romain Dolbeau, Jorge Alejandro Nocua Cifuentes, Luis Bertran Alvarez, Dirk Pleiter, Estela Suarez

Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

2021

Multilevel simulation-based co-design of next generation HPC microprocessors.

Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau

Proceedings of the 2021 International Workshop on Performance Modeling, 2021

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors.

Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Evolution of application-specific cache mappings.

Nam Ho, Paul Kaufmann, Marco Platzner

Int. J. Hybrid Intell. Syst., 2020

2019

Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor.

Nam Ho, Paul Kaufmann, Marco Platzner

Proceedings of the 11th International Conference on Soft Computing and Pattern Recognition (SoCPaR 2019), 2019

2018

FPGA-based reconfigurable cache mapping schemes: design and optimization.

Nam Ho

PhD thesis, 2018

2017

Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.

Nam Ho, Paul Kaufmann, Marco Platzner

Proceedings of the International Conference on Field Programmable Technology, 2017

Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor.

Nam Ho, Ishraq Ibne Ashraf, Paul Kaufmann, Marco Platzner

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches.

Paul Kaufmann, Nam Ho, Marco Platzner

Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2015

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions.

Andrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enhancing an x86_64 multi-core architecture with data-flow execution support.

Nam Ho, Andrea Mondelli, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi

Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings.

Nam Ho, Abdullah Fathi Ahmed, Paul Kaufmann, Marco Platzner

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure.

Nam Ho, Paul Kaufmann, Marco Platzner

Proceedings of the 2014 IEEE International Conference on Evolvable Systems, 2014

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms.

Nam Ho, Paul Kaufmann, Marco Platzner

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2010

MemMON: run-time off-chip detection for memory access violation in embedded systems.

Nam Ho, Anh-Vu Dinh-Duc

Proceedings of the 2010 Symposium on Information and Communication Technology, 2010