Nalesh S

Affiliations:
  • Cochin University of Science and Technology, Department of Electronics, India


According to our database1, Nalesh S authored at least 26 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A physically unclonable function architecture with multiple responses on FPGA.
Int. J. Embed. Syst., 2023

MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Approximate CNN on FPGA Using Toom-Cook Multiplier.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
Adiabatic Physical Unclonable Function Using Cross-Coupled Pair.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021
Hardware Acceleration of SpMV Multiplier for Deep Learning.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Fast Booth Multipliers Using Approximate 4: 2 Compressors.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2019
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Radix-4<sup>3</sup> based two-dimensional FFT architecture with efficient data reordering scheme.
IET Comput. Digit. Tech., 2019

UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Efficient Hardware Acceleration of Convolutional Neural Networks.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018
A Hardware Architecture for Radial Basis Function Neural Network Classifier.
IEEE Trans. Parallel Distributed Syst., 2018

Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Two dimensional FFT architecture based on radix-4<sup>3</sup> algorithm with efficient output reordering.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017
Energy aware synthesis of application kernels through composition of data-paths on a CGRA.
Integr., 2017

2016
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture.
J. Low Power Electron., 2015

Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.
Proceedings of the 28th International Conference on VLSI Design, 2015

Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Compiling HPC Kernels for the REDEFINE CGRA.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.
J. Syst. Archit., 2014

Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2013
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013


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