Nakul Narang

According to our database, Nakul Narang authored at least 7 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies.

Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2019

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang

IEEE J. Solid State Circuits, 2019

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.

Marc Erett, Declan Carey, Ronan Casey, James Hudner, Kevin Geary, Ted Lee, Mayank Raj, Hongtao Zhang, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Nakul Narang, Pedro Neto, Bruce Xu, Winson Lin, Kee Hian Tan, Yohan Frans, Ken Chang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 112-GB/S PAM4 Transmitter in 16NM FinFET.

Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.

Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS.

Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ping-Chuan Chiang, Ken Chang

IEEE J. Solid State Circuits, 2017

2016

A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.

Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ken Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016