Nagendra Krishnapura

IEEE J. Solid State Circuits, September, 2024

Analysis of Signal Transmission through Time-Varying Inductively Coupled Links.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Bandpass Filter and Oscillator ICs with THD ppd for Testing High-Resolution ADCs.

[BibT_eX]

[DOI]

Subha Sarkar

Rajat Agarwal

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs.

[BibT_eX]

[DOI]

Aditya Narayanan

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis.

[BibT_eX]

[DOI]

Sumit Kumar

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched G<sub>m</sub> for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier.

[BibT_eX]

[DOI]

Paramita Banerjee

IEEE J. Solid State Circuits, 2022

2021

Effects of AC Response Imperfections in True-Time-Delay Lines.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

2020

Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems.

[BibT_eX]

[DOI]

Chithra

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

High Linearity Transmit Power Mixers Using Baseband Current Feedback.

[BibT_eX]

[DOI]

M. V. Praveen

IEEE J. Solid State Circuits, 2020

A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems.

[BibT_eX]

[DOI]

Purnendu Bhattaru

Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

A 52dB Spurious-Free Dynamic Range Ku-Band LNA-Mixer in a 130nm SiGe BiCMOS Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Noise Shaping Techniques for SNR Enhancement in SAR Analog to Digital Converters.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Maximizing the Data Rate of an Inductively Coupled Chip-to-Chip Link by Resetting the Channel State Variables.

[BibT_eX]

[DOI]

Anoop Narayan Bhat

Subhashish Mukherjee

Kumar Anurag Shrivastava

Madhulatha Bonu

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS Using a 4-Port Dual-Mode Resonator for 5G Radios.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Static Phase Offset Reduction Technique for Delay Locked Loops.

[BibT_eX]

[DOI]

Chithra

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter.

[BibT_eX]

[DOI]

Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018

Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion.

[BibT_eX]

[DOI]

Debasish Behera

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Low 1/f<sup>3</sup> Phase Noise Quadrature LC VCOs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

An Automatic LO Leakage Calibration Method for Class-AB Power Mixer Based RF Transmitters.

[BibT_eX]

[DOI]

M. V. Praveen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13µm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A Low Power Multi-channel Input Delta-Sigma ADC without Reset.

[BibT_eX]

[DOI]

Ashwin Kumar Siva Kumar

Debasish Behera

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS.

[BibT_eX]

[DOI]

Subhashish Mukherjee

Anoop Narayan Bhat

Kumar Anurag Shrivastava

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Optimum scaling of stages in a frequency divider chain for best jitter FoM.

[BibT_eX]

[DOI]

Sumit Kumar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Session 12-Analog techniques I.

[BibT_eX]

[DOI]

Ken Suyama

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

A 12.5 mW, 11.1 nV√Hz, -115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 µm CMOS.

[BibT_eX]

[DOI]

K. S. Rakshitdatta

Yujendra Mitikiri

IEEE Trans. Circuits Syst. II Express Briefs, 2016

Demystifying Time Varying Circuits and Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A tail-resonance calibration technique for wide tuning range LC VCOs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback.

[BibT_eX]

[DOI]

K. S. Rakshitdatta

Proceedings of the 28th International Conference on VLSI Design, 2015

Accurate Constant Transconductance Generation without Off-Chip Components.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Gain enhanced high frequency OTA with on-chip tuned negative conductance load.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

A Model-Agnostic Technique for Simulating Per-Element Distortion Contributions.

[BibT_eX]

[DOI]

K. S. Rakshitdatta

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Tutorial T6A: Pedagogy of Negative Feedback Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter.

[BibT_eX]

[DOI]

Debasish Behera

Proceedings of the ESSCIRC 2014, 2014

2012

A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

Synthesis based introduction to opamps and phase locked loops.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Introducing negative feedback with an integrator as the central element.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

On Pulse Position Modulation and Its Application to PLLs for Spur Reduction.

[BibT_eX]

[DOI]

Chembiyan Thambidurai

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps.

[BibT_eX]

[DOI]

Abhishek Agrawal

Sameer Singh

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Electronic time stretching for fast digitization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators.

[BibT_eX]

[DOI]

Vikas Singh

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Spur reduction in wideband PLLs by random positioning of charge pump current pulses.

[BibT_eX]

[DOI]

Chembiyan Thambidurai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 100 µW Decimator for a 16 bit 24 kHz bandwidth Audio ΔΣ Modulator.

[BibT_eX]

[DOI]

Shankar Parameswaran

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A Comparison of Approaches to Carrier Generation for Zigbee Transceivers.

[BibT_eX]

[DOI]

Leburu Manojkumar

Arun Mohan

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Negative Feedback System and Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications.

[BibT_eX]

[DOI]

Ramalingam Pandarinathan

Prabu Sankar

IEEE J. Solid State Circuits, 2008

Oversampling Analog-to-Digital Converter Design.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 90μW 15-bit ΔΣ ADC for digital audio.

[BibT_eX]

[DOI]

Ramalingam Pandarinathan

Prabu Sankar

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2003

Micropower low-voltage analog filter in a digital CMOS process.

[BibT_eX]

[DOI]

Yannis P. Tsividis

IEEE J. Solid State Circuits, 2003

2001

Noise and power reduction in filters through the use of adjustable biasing.

[BibT_eX]

[DOI]

Yannis P. Tsividis

IEEE J. Solid State Circuits, 2001

2000

A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS.

[BibT_eX]

[DOI]