Nagatoshi Ohki

According to our database, Nagatoshi Ohki authored at least 6 papers between 1991 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

1996

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.

Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure

IEEE J. Solid State Circuits, 1996

1995

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL.

Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, November, 1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.

Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida

IEEE J. Solid State Circuits, April, 1995

1993

A 16-Mb CMOS SRAM with a 2.3- mu m² single-bit-line memory cell.

Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki

IEEE J. Solid State Circuits, November, 1993

1992

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki

IEEE J. Solid State Circuits, March, 1992

1991

Quasi-complementary BiCMOS for sub-3-V digital circuits.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, November, 1991