Nagatoshi Ohki

According to our database1, Nagatoshi Ohki authored at least 5 papers between 1992 and 1996.

Collaborative distances:

Timeline

1992
1993
1994
1995
1996
0
1
2
3
1
2
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996

1995
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL.
IEEE J. Solid State Circuits, November, 1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.
IEEE J. Solid State Circuits, April, 1995

1993
A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell.
IEEE J. Solid State Circuits, November, 1993

1992
3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules.
IEEE J. Solid State Circuits, March, 1992


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