Nagarajan Venkateswaran

According to our database, Nagarajan Venkateswaran authored at least 19 papers between 2003 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores.

Nagarajan Venkateswaran, Kartik Lakshminarasimhan, Akash Sridhar, Prashanth Thinakaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Aswin Sridharan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012

Compilation Accelerator on Silicon.

Nagarajan Venkateswaran, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Rajagopal Hariharan, Bharanidharan Vasudevan, Nachiappan Chidambaram Nachiappan, Karthikeyan P. Saravanan, Aswin Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V. S. Vignesh, Ravindhiran Mukundrajan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

SCOC IP Cores for Custom Built Supercomputing Nodes.

Nagarajan Venkateswaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Vigneshwaran Sankaran, Bharanidharan Vasudevan, Ravindhiran Mukundrajan, Nachiappan Chidambaram Nachiappan, Aswin Sridharan, Karthikeyan P. Saravanan, Vignesh Adhinarayanan, Vignesh Veppur Sankaranarayanan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2010

Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions.

Nagarajan Venkateswaran, Karthikeyan P. Saravanan, Nachiappan Chidambaram Nachiappan, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009

Towards modeling and integrated design automation of supercomputing clusters (MIDAS).

Nagarajan Venkateswaran, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan

Comput. Sci. Res. Dev., 2009

A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient.

Nagarajan Venkateswaran, Ravindhiran Mukundrajan, Mrigank Sharma, Badrinarayanan Ravi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system.

Nagarajan Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, V. Sangkar, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, M. Thyagarajan

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Design for Testability of Functional Cores in High Performance Node Architectures.

Nagarajan Venkateswaran, Karthik Chandrasekar, Shrikanth Ganapathy

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

Future generation supercomputers II: a paradigm for cluster architecture.

Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan

SIGARCH Comput. Archit. News, 2007

Future generation supercomputers I: a paradigm for node architecture.

Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan

SIGARCH Comput. Archit. News, 2007

DNA Based Evolutionary Approach for Microprocessor Design Automation.

Nagarajan Venkateswaran, Arjun Kumeresh, Harish Chandran

Proceedings of the Adaptive and Natural Computing Algorithms, 8th International Conference, 2007

2006

PASCOM: Power Model for Supercomputers.

Arrvindh Shriraman, Nagarajan Venkateswaran, Niranjan Soundararajan

Proceedings of the Architecture of Computing Systems, 2006

2005

Fault tolerant bus architecture for deep submicron based processors.

N. Venkateswaran, S. Balaji, V. Sridhar

SIGARCH Comput. Archit. News, 2005

Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance.

Nagarajan Venkateswaran, Arrvindh Shriraman, Niranjan Soundararajan

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Memory in processor: a novel design paradigm for supercomputing architectures.

Nagarajan Venkateswaran, Aditya Krishnan, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan

SIGARCH Comput. Archit. News, 2004

Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design.

N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level.

N. Venkateswaran, Krishna Bharath

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Analysis of Bit Transition Count for EDAC Encoded FSM.

N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies.

N. Venkateswaran, C. Chandramouli

Proceedings of the Evolvable Systems: From Biology to Hardware, 2003