Nagadastagiri Challapalle

Orcid: 0000-0003-3324-2009

According to our database1, Nagadastagiri Challapalle authored at least 13 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Fusing In-storage and Near-storage Acceleration of Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., January, 2024

GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.
IEEE Trans. Emerg. Top. Comput., 2024

2023
Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph.
CoRR, 2022

ISKEVA: in-SSD key-value database engine for video analytics applications.
Proceedings of the LCTES '22: 23rd ACM SIGPLAN/SIGBED International Conference on Languages, 2022

Performance Evaluation of Video Analytics Workloads on Emerging Processing-In-Memory Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks.
J. Signal Process. Syst., 2020

Adaptive Neural Network Architectures for Power Aware Inference.
IEEE Des. Test, 2020

X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

IMC-Sort: In-Memory Parallel Sorting Architecture using Hybrid Memory Cube.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020


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