Naga Durga Prasad Avirneni

According to our database, Naga Durga Prasad Avirneni authored at least 6 papers between 2007 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors.

Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani

IEEE Trans. Computers, 2016

Managing contamination delay to improve Timing Speculation architectures.

Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani

PeerJ Prepr., 2016

2014

Countering Power Analysis Attacks UsingReliable and Aggressive Designs.

Naga Durga Prasad Avirneni, Arun K. Somani

IEEE Trans. Computers, 2014

2012

Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs.

Naga Durga Prasad Avirneni, Arun K. Somani

IEEE Trans. Computers, 2012

2009

Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems.

Naga Durga Prasad Avirneni, Viswanathan Subramanian, Arun K. Somani

Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

2007

Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning.

Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007