Nafiul Siddique

Orcid: 0000-0002-9172-0040

According to our database1, Nafiul Siddique authored at least 9 papers between 2014 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2018
A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC.
J. Supercomput., 2018

2017
The time-varying nature of cache utilization: A case study on the Mantevo and Apex benchmarks.
Proceedings of the 2017 IEEE SmartWorld, 2017

Local memory store (LMStr): A hardware controlled shared scratchpad for multicores.
Proceedings of the 2017 IEEE SmartWorld, 2017

Spare block cache (SprBlk): Fault resilience and reliability at low voltages.
Proceedings of the 2017 IEEE SmartWorld, 2017

LMStr: exploring shared hardware controlled scratchpad memory for multicores.
Proceedings of the International Symposium on Memory Systems, 2017

SprBlk cache: enabling fault resilience at low voltages.
Proceedings of the International Symposium on Memory Systems, 2017

Can Architecture Design Help Eliminate Some Common Vulnerabilities?
Proceedings of the 14th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, 2017

2016
LMStr: Local memory store the case for hardware controlled scratchpad memory for general purpose processors.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016

2014
Insight into Application Performance Using Application-Dependent Characteristics.
Proceedings of the High Performance Computing Systems. Performance Modeling, Benchmarking, and Simulation, 2014


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