Nadesh Ramanathan

Orcid: 0000-0001-9083-8349

According to our database1, Nadesh Ramanathan authored at least 11 papers between 2014 and 2022.

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Bibliography

2022
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis.
ACM Trans. Design Autom. Electr. Syst., 2022

2021
Global Analysis of C Concurrency in High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Formal verification of high-level synthesis.
Proc. ACM Program. Lang., 2021

Fuzzing High-Level Synthesis Tools.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

An Empirical Study of the Reliability of High-Level Synthesis Tools.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
Precise Pointer Analysis in High-Level Synthesis.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2018
Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware.
IEEE Trans. Computers, 2018

Concurrency-Aware Thread Scheduling for High-Level Synthesis.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Hardware Synthesis of Weakly Consistent C Concurrency.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
A Case for Work-stealing on FPGAs with OpenCL Atomics.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2014
A case for leveraging 802.11p for direct phone-to-phone communications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014


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