Nadereh Hatami

Orcid: 0000-0002-0550-5695

According to our database1, Nadereh Hatami authored at least 12 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip.
IEEE Trans. Computers, 2017

2014
Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation.
ACM Trans. Design Autom. Electr. Syst., 2014

On Covering Structural Defects in NoCs by Functional Tests.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012
Efficient system-level aging prediction.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Efficient multi-level fault simulation of HW/SW systems for structural faults.
Sci. China Inf. Sci., 2011

2010
System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Sign Language synthesis using hand motion acquisition.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Communication interface synthesis from TLM 2.0 to RTL.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Test infrastructures evaluation at transaction level.
Proceedings of the 2009 IEEE International Test Conference, 2009

System Level Testing via TLM 2.0 Debug Transport Interface.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
An advanced method for synthesizing TLM2-based interfaces.
Proceedings of the 2008 East-West Design & Test Symposium, 2008


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