Nader Rafla

Affiliations:
  • Boise State University, Electrical and Computer Engineering Department, ID, USA


According to our database1, Nader Rafla authored at least 23 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Enhanced Hardware Trojan Detection in Chips By Reducing Linearity Between Features.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

2022
Efficient mitigation technique for Black Hole router attack in Network-on-Chip.
Microprocess. Microsystems, October, 2022

Energy-Efficient Black Hole Router Detection in Network-on-Chip.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

2021
Hardware implementation of Multi-Rate input SoftMax activation function.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020
A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA.
Microprocess. Microsystems, 2020

A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching.
Microprocess. Microsystems, 2020

Evaluating and Improving Child-Directed Automatic Speech Recognition.
Proceedings of The 12th Language Resources and Evaluation Conference, 2020

HLS Implementation of Linear Discriminant Analysis Classifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Detection and prevention protocol for black hole attack in network-on-chip.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Analysis of Black Hole Router Attack in Network-on-Chip.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS).
Proceedings of 34th International Conference on Computers and Their Applications, 2019

2018
Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Routing Aware and Runtime Detection for Infected Network-on-Chip Routers.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
High level synthesis using vivado HLS for optimizations of SHA-3.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
Zynq-based SoC implementation of an induction machine control algorithm.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2015
Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2013
An automated embedded computer vision system for object measurement.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
Welcome to the 55<sup>th</sup> IEEE international midwest symposium on circuits and systems (MWSCAS 2012).
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012


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