Nader Rafla
Affiliations:- Boise State University, Electrical and Computer Engineering Department, ID, USA
According to our database1,
Nader Rafla
authored at least 23 papers
between 2012 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
2023
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
2022
Microprocess. Microsystems, October, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
2020
A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA.
Microprocess. Microsystems, 2020
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching.
Microprocess. Microsystems, 2020
Proceedings of The 12th Language Resources and Evaluation Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS).
Proceedings of 34th International Conference on Computers and Their Applications, 2019
2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
2015
Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
Welcome to the 55<sup>th</sup> IEEE international midwest symposium on circuits and systems (MWSCAS 2012).
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012