Nader Kalantari

According to our database1, Nader Kalantari authored at least 3 papers between 2006 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
A Multichannel Serial Link Receiver With Dual-Loop Clock-and-Data Recovery and Channel Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2007
All-CMOS High-Speed CML Gates with Active Shunt-Peaking.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Design of CMOS Ternary Latches.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006


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