Nabil Badereddine
According to our database1,
Nabil Badereddine
authored at least 23 papers
between 2005 and 2014.
Collaborative distances:
Collaborative distances:
Timeline
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
0
1
2
3
4
5
6
7
1
1
1
6
2
3
5
2
2
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2014
J. Electron. Test., 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs.
Proceedings of the 2013 IEEE International Test Conference, 2013
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability.
Proceedings of the 18th IEEE European Test Symposium, 2013
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
J. Electron. Test., 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
Proceedings of the 47th Design Automation Conference, 2010
2008
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electron. Test., 2008
2006
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.
Proceedings of the Integrated Circuit and System Design, 2005