N. Sathisha

According to our database, N. Sathisha authored at least 4 papers between 2011 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

A robust 8T FinFET SRAM cell with improved stability for low voltage applications.

C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2013

DTCWT based high capacity steganography using coefficient replacement and adaptive scaling.

N. Sathisha, R. Priya, K. Suresh Babu, K. B. Raja, K. R. Venugopal, L. M. Patnaik

Proceedings of the Sixth International Conference on Machine Vision, 2013

2012

An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs.

Ankur Goel, Donald Evans, Richard Stephani, Venkateswara Reddy, Dharmendra Rai, Veerabadra Chary, N. Sathisha

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

Covariance Based Steganography Using DCT.

N. Sathisha, K. Suresh Babu, K. B. Raja, K. R. Venugopal, Lalit M. Patnaik

Proceedings of the Advances in Computing and Communications, 2011