N. S. Nagaraj

According to our database, N. S. Nagaraj authored at least 28 papers between 1992 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Moore's Law: another casualty of the financial meltdown?

Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork

Proceedings of the 46th Design Automation Conference, 2009

2008

DFM in practice: hit or hype?

Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh

Proceedings of the 45th Design Automation Conference, 2008

2006

SmartExtract: Accurate Capacitance Extraction for SOC Designs.

Usha Narasimha, Anthony M. Hill, N. S. Nagaraj

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Interconnect Process Variations: Theory and Practice.

N. S. Nagaraj

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Statistical Analysis of Capacitance Coupling Effects on Delay and Noise.

Usha Narasimha, Binu Abraham, N. S. Nagaraj

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Optimizing Interconnect for Performance in Standard Cell Library.

Dharin Shah, Kothamasu Siva, G. Girishankar, N. S. Nagaraj

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

The Impact of Inductance on Transients Affecting Gate Oxide Reliability.

N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Dealing with interconnect process variations.

N. S. Nagaraj

Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

BEOL variability and impact on RC extraction.

N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill

Proceedings of the 42nd Design Automation Conference, 2005

2004

Interconnect Modeling for Copper/Low-k Technologies.

N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A 800 MHz System-on-Chip for Wireless Infrastructure Applications.

Sanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Autonomic Incident Manager for Enterprise Applications.

Renuka Sindhgatta, Swaminathan Natarajan, Krishnakumar Pooloth, Colin Pinto, N. S. Nagaraj

Proceedings of the Grid and Cooperative Computing, 2004

2003

Benchmarks for Interconnect Parasitic Resistance and Capacitance.

N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

A 600-MHz VLIW DSP.

Sanjive Agarwala, Timothy Anderson, Anthony M. Hill, M. D. Ales, Raguram Damodaran, Paul Wiley, Steven Mullinnix, J. Leach, Anthony Lell, Michael Gill, Arjun Rajagopal, Abhijeet Chachad, M. Agarwala, John Apostol, Manjeri Krishnan, Duc Bui, Quang An, N. S. Nagaraj, Tod Wolf, T. T. Elappuparackal

IEEE J. Solid State Circuits, 2002

Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification.

N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Interconnect Modeling for Timing, Signal Integrity and Reliability.

Narain Arora, N. S. Nagaraj

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000

A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs.

N. S. Nagaraj, Frank Cano, Duane Young, Deepak Vohra, Manoj Das

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Full-Chip Signal Interconnect Analysis for Electromigration Reliability.

Steffen Rochel, N. S. Nagaraj

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Enabling DIR(Designing-In-Reliability) through CAD Capabilities.

Wonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

When bad things happen to good chips (panel session).

N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang

Proceedings of the 37th Conference on Design Automation, 2000

1998

Taming Noise in Deep Submicron Digital Integrated Circuits (Panel).

N. S. Nagaraj, Kenneth L. Shepard, Takahide Inone

Proceedings of the 35th Conference on Design Automation, 1998

A Practical Approach to Static Signal Electromigration Analysis.

N. S. Nagaraj, Frank Cano, Haldun Haznedar, Duane Young

Proceedings of the 35th Conference on Design Automation, 1998

1997

Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century.

R. G. Bushroe, S. DasGupta, A. Dengi, P. Fisher, S. Grout, G. Ledenbach, N. S. Nagaraj, R. Steele

Proceedings of the 1997 International Symposium on Physical Design, 1997

1994

Approximate Computation of Signal Characteristics of On-chip RC Interconnect Trees.

N. S. Nagaraj, Paul Krivacek, Mark Harward

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

A New Optimizer for Performance Optimization of Integrated Circuits by Device Sizing.

N. S. Nagaraj

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A New Optimizer for Performance Optimization of Analog Integrated Circuits.

N. S. Nagaraj

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits.

S. Nagaraj, N. Padmini, N. S. Nagaraj, R. Ramesh, V. Sachidanand

Proceedings of the Fifth International Conference on VLSI Design, 1992

OPSYN - OASYS Based Pseudosynthesis Tool.

N. S. Nagaraj

Proceedings of the Fifth International Conference on VLSI Design, 1992