N. S. Murty

According to our database, N. S. Murty authored at least 9 papers between 1997 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC.

M. Vinodhini, N. S. Murty, T. K. Ramesh

IEEE Access, 2020

2018

Reliable low power NoC interconnect.

M. Vinodhini, N. S. Murty

Microprocess. Microsystems, 2018

Performance of Vector Fitting Algorithm Applied to Bandpass and Baseband Systems.

K. Vrinda, N. S. Murty, Dhanesh G. Kurup

Circuits Syst. Signal Process., 2018

Multi-Bit Error Correction Coding with Crosstalk Avoidance Using Parity Sharing Technique for NoC.

Supriya Rajagopal, M. Vinodhini, N. S. Murty

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Joint Crosstalk Avoidance with Multiple Bit Error Correction Coding Technique for NoC Interconnect.

T. Siva Teja, T. Sai Kiran, T. V. V. Satya Narayana, M. Vinodhini, N. S. Murty

Proceedings of the 2018 International Conference on Advances in Computing, 2018

Delay based Physical Unclonable Function for Hardware Security and Trust.

Kolasani Sahithi, N. S. Murty

Proceedings of the 2018 International Conference on Advances in Computing, 2018

2017

Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique.

Rajani Suthar, Kirti S. Pande, N. S. Murty

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2001

IBM's Blue Logic Design Methodology-Circuits and Physical Design.

Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

1997

Effective Heuristics for Timing Driven Constructive Placement.

R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997