N. S. Aswathy

Orcid: 0000-0001-7580-2065

According to our database1, N. S. Aswathy authored at least 9 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories.
J. Syst. Archit., 2024

Write Intensity based Foresightful Page Migration for Hybrid memories.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems.
ACM Trans. Embed. Comput. Syst., March, 2023

WIB-SAR: Write Intensity Based Selective Address Remapping.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

AGRAS: Aging and memory request rate aware scheduler for PCM memories.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems.
Proceedings of the 27th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2021

2017
Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017


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