N. Ranganathan

Proceedings of the 25th International Conference on VLSI Design, 2012

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles.

[BibT_eX]

[DOI]

Matthew Morrison

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure.

[BibT_eX]

[DOI]

Matthew Morrison

Matthew Lewandowski

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates.

[BibT_eX]

[DOI]

Saurabh Kotiyal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Run-time power-gating in caches of GPUs for leakage energy savings.

[BibT_eX]

[DOI]

Yue Wang

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Mach-Zehnder interferometer based design of all optical reversible binary adder.

[BibT_eX]

[DOI]

Saurabh Kotiyal

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Redundancy Mining for Soft Error Detection in Multicore Processors.

[BibT_eX]

[DOI]

Ransford Hyman Jr.

IEEE Trans. Computers, 2011

Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits

[BibT_eX]

[DOI]

CoRR, 2011

Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures.

[BibT_eX]

[DOI]

Matthew Morrison

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A new reversible design of BCD adder.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

An Instruction-Level Energy Estimation and Optimization Methodology for GPU.

[BibT_eX]

[DOI]

Yue Wang

Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

2010

Timing-Based Placement Considering Uncertainty Due to Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets.

[BibT_eX]

[DOI]

IEEE Trans. Knowl. Data Eng., 2010

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2010

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009

A Framework for Power-Gating Functional Units in Embedded Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy.

[BibT_eX]

[DOI]

Soontae Kim

IEEE Trans. Very Large Scale Integr. Syst., 2009

Variation-aware multimetric optimization during gate sizing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Exploring Compiler Optimizations for Enhancing Power Gating.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Strategy for Soft Error Reduction in Multi Core Designs.

[BibT_eX]

[DOI]

Ransford Hyman Jr.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A VLSI System Architecture for Optical Flow Computation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Compiler-directed leakage reduction in embedded microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

2008

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.

[BibT_eX]

[DOI]

J. E. Harlow

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

An expected-utility based approach to variation aware VLSI optimization under scarce information.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

A microeconomic approach to multi-objective spatial clustering.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Pattern Recognition (ICPR 2008), 2008

Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A linear programming formulation for security-aware gate sizing.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Multievent Crisis Management Using Noncooperative Multistep Games.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

A Sequential Distinguisher for Covert Channel Identification.

[BibT_eX]

[DOI]

K. P. Subbalakshmi

Rajarathnam Chandramouli

Int. J. Netw. Secur., 2007

VLSI architecture and chip for combined invisible robust and fragile watermarking.

[BibT_eX]

[DOI]

Elias Kougianos

IET Comput. Digit. Tech., 2007

A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Statistical Gate Sizing for Yield Enhancement at Post Layout Level.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Integrated Gate and Wire Sizing at Post Layout Level.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Variation Aware Timing Based Placement Using Fuzzy Programming.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A microeconomic approach to multi-robot team formation.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE/RSJ International Conference on Intelligent Robots and Systems, October 29, 2007

Improving the reliability of on-chip L2 cache using redundancy.

[BibT_eX]

[DOI]

Soontae Kim

Proceedings of the 25th International Conference on Computer Design, 2007

2006

ILP models for simultaneous energy and transient power minimization during behavioral synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks.

[BibT_eX]

[DOI]

Karthikeyan Lingasubramanian

ACM Trans. Design Autom. Electr. Syst., 2006

A dual voltage-frequency VLSI chip for image watermarking in DCT domain.

[BibT_eX]

[DOI]

Karthikeyan Balakrishnan

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

An Automatic Code Generation Tool for Partitioned Software in Distributed Systems.

[BibT_eX]

[DOI]

Viswanath Sairaman

Neeta S. Singh

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.

[BibT_eX]

[DOI]

Aswath Oruganti

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Social Fairness in Multi-Emergency Resource Management.

[BibT_eX]

[DOI]

Proceedings of the Disaster Preparedness and Recovery: IEEE International Symposium on Technology and Society, 2006

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A novel approach for variation aware power minimization during gate sizing.

[BibT_eX]

[DOI]

Justin E. Harlow III

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2005

A VLSI architecture for visible watermarking in a secure still digital camera (S2/DC) design (Corrected)*.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

A VLSI architecture for watermarking in a secure still digital camera (S2DC) design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency.

[BibT_eX]

[DOI]

Karthikeyan Balakrishnan

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.

[BibT_eX]

[DOI]

Karthikeyan Lingasubramanian

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

A framework for energy and transient power reduction during behavioral synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

LECTOR: a technique for leakage reduction in CMOS circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Stochastic channel-adaptive rate control for wireless video transmission.

[BibT_eX]

[DOI]

Koduvayur P. Subbalakshmi

Pattern Recognit. Lett., 2004

Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Control and Data Flow Graph Extraction for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003

A game theoretic approach for power optimization during behavioral synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Petri net modeling of gate and interconnect delays for power estimation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Routing on field-programmable switch matrices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Multiterminal net routing for partial crossbar-based multi-FPGA systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Switching activity estimation of VLSI circuits using Bayesian networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A Game-Theoretic Approach for Binding in Behavioral Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Energy Efficient Scheduling for Datapath Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Peak Power Minimization Through Datapath Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

An ILP-based scheduling scheme for energy efficient high performance datapath synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Transient power minimization through datapath scheduling in multiple supply voltage environment.

[BibT_eX]

[DOI]

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Simultaneous peak and average power minimization during datapath scheduling for DSP processors.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A low power scheduler using game theory.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002

Least-square estimation of average power in digital CMOS circuits.

[BibT_eX]

[DOI]

Srinath Chavali

IEEE Trans. Very Large Scale Integr. Syst., 2002

A comparative study of bidirectional ring and crossbar interconnection networks.

[BibT_eX]

[DOI]

Hitoshi Oi

Comput. Electr. Eng., 2002

A Real Delay Switching Activity Simulator Based on Petri Net Modeling.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Datapath Scheduling using Dynamic Frequency Clocking.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Power estimation of sequential circuits using hierarchical colored hardware petri net modeling.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A VLSI Architecture for Object Recognition Using Tree Matching.

[BibT_eX]

[DOI]

K. Sitaraman

Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001

IDUTC: an intelligent decision-making system for urban traffic-control applications.

[BibT_eX]

[DOI]

IEEE Trans. Veh. Technol., 2001

A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

An intelligent system for failure detection and control in an autonomous underwater vehicle.

[BibT_eX]

[DOI]

R. Sathyamurthy

IEEE Trans. Syst. Man Cybern. Part A, 2001

Context-based lossless image coding using EZW framework.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2001

Average Power in Digital CMOS Circuits using Least Square Estimation.

[BibT_eX]

[DOI]

Srinath Chavali

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Utilization of cache area in on-chip multiprocessor.

[BibT_eX]

[DOI]

Hitoshi Oi

Microprocess. Microsystems, 2000

VBR video traffic management using a predictor-based architecture.

[BibT_eX]

[DOI]

Ravi Sankar

Comput. Commun., 2000

CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis.

[BibT_eX]

[DOI]

Vamsi K. Srikantam

Srikanth Srinivasan

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Routing on Switch Matrix Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Design Partitioning on Single-Chip Emulation Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 9th Heterogeneous Computing Workshop, 2000

1999

A tree-matching chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

Computation of lower bounds for switching activity using decision theory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

Performance analysis of wavelets in embedded zerotree-based lossless image coding schemes.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1999

Computing the bivariate Gaussian probability integral.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 1999

Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM Symposium on Applied Computing, 1999

Context based lossless intraframe coding of video sequence using embedded zerotree wavelets.

[BibT_eX]

[DOI]

Veeraraghavan N. Ramaswamy

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Context modeling of wavelet coefficients in EZW-based lossless image coding.

[BibT_eX]

[DOI]

Kamesh Namuduri

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata.

[BibT_eX]

[DOI]

Proceedings of the 8th Heterogeneous Computing Workshop, 1999

Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Tuning Branch Predictors to Support Virtual Method Invocation in Java.

[BibT_eX]

[DOI]

Proceedings of the 5th USENIX Conference on Object-Oriented Technologies & Systems, 1999

1998

A linear array processor with dynamic frequency clocking for image processing applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 1998

Adaptive quantization and fast error-resilient entropy coding for image transmission.

[BibT_eX]

[DOI]

Shivaraman J. Ramadoss

IEEE Trans. Circuits Syst. Video Technol., 1998

A VLSI Architecture for Approximate Tree Matching.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

A generalized sequential sign detector for binary hypothesis testing.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 1998

SMAC: A VLSI Architecture for Scene Matching.

[BibT_eX]

[DOI]

Raguveer Venkatesan

Real Time Imaging, 1998

A Forum for VLSI Practitioners.

[BibT_eX]

[DOI]

Computer, 1998

Adaptive VBR video traffic management for higher utilization of ATM networks.

[BibT_eX]

[DOI]

Ravi Sankar

Comput. Commun. Rev., 1998

A VLSI ATM Switch Architecture for VBR Traffic.

[BibT_eX]

[DOI]

Rajat Anand

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Rate control for a video coder using learning automata.

[BibT_eX]

[DOI]

Sharad Kumar

Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, 1998

An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks.

[BibT_eX]

[DOI]

Ravi Sankar

Proceedings of the Third IEEE Symposium on Computers and Communications (ISCC 1998), June 30, 1998

Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission.

[BibT_eX]

[DOI]

Sharad Kumar

Proceedings of the 1998 IEEE International Conference on Image Processing, 1998

A simple adaptive wormhole routing algorithm for MIMD systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

A scene-based generalized Markov chain model for VBR video traffic.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE International Conference on Communications, 1998

A Methodology for High Level Power Estimation and Exploration.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Object-Oriented Architectural Support for a Java Processor.

[BibT_eX]

[DOI]

Ravi Gadekarla

Proceedings of the ECOOP'98, 1998

Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission.

[BibT_eX]

[DOI]

Shivaraman J. Ramadoss

Proceedings of the Data Compression Conference, 1998

1997

C3L: A Chip for Connected Component Labeling.

[BibT_eX]

[DOI]

Ashley Rasquinha

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor.

[BibT_eX]

[DOI]

Hitoshi Oi

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

SUBGEN: a genetic approach for subcircuit extraction.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Mapping and parallel implementation of Bayesian belief networks.

[BibT_eX]

[DOI]

Nina Saxena

Sudeep Sarkar

Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

An intelligent system architecture for urban traffic control applications.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

A dynamic frequency linear array processor for image processing.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Pattern Recognition, 1996

Lossless image compression using wavelet decomposition.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Pattern Recognition, 1996

SVBS: a high-resolution medical image compression algorithm using slicing with variable block size segmentation.

[BibT_eX]

[DOI]

Hooman Rashedi

Proceedings of the 13th International Conference on Pattern Recognition, 1996

A VLSI system architecture for lossless image compression.

[BibT_eX]

[DOI]

S. B. Aruru

Proceedings of the 13th International Conference on Pattern Recognition, 1996

SIMD algorithms for single link and complete link pattern clustering.

[BibT_eX]

[DOI]

S. Arumugavelu

Proceedings of the 13th International Conference on Pattern Recognition, 1996

PANTHER: a parallel neuro-systolic architecture for real-time processing.

[BibT_eX]

[DOI]

Proceedings of International Conference on Neural Networks (ICNN'96), 1996

DFLAP: a dynamic frequency linear array processor.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

A VLSI array architecture with dynamic frequency clocking.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

A VLSI chip for image compression using variable block size segmentation.

[BibT_eX]

[DOI]

S. B. Aruru

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

A linear systolic algorithm and architecture for convex bipartite matching.

[BibT_eX]

[DOI]

Rajesh Chandra

Proceedings of the 3rd International Conference on High Performance Computing, 1996

A VLSI System Architecture For Real-Time Intelligent Decision Making.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995

A high speed systolic architecture for labeling connected components in an image.

[BibT_eX]

[DOI]

S. Subramaniam

IEEE Trans. Syst. Man Cybern., 1995

A lossless image compression algorithm using variable block size segmentation.

[BibT_eX]

[DOI]

Steve G. Romaniuk

IEEE Trans. Image Process., 1995

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard.

[BibT_eX]

[DOI]

Proc. IEEE, 1995

CASM: A VLSI Chip for Approximate String Matching.

[BibT_eX]

[DOI]

Klinton Remedios

IEEE Trans. Pattern Anal. Mach. Intell., 1995

VLSI Architectures for High-Speed Range Estimation.

[BibT_eX]

[DOI]

Ramesh C. Jain

IEEE Trans. Pattern Anal. Mach. Intell., 1995

PMAC: A Polygon Matching Chip.

[BibT_eX]

[DOI]

Int. J. Pattern Recognit. Artif. Intell., 1995

Conference Reports.

[BibT_eX]

Sharad C. Seth

IEEE Des. Test Comput., 1995

JAGUAR: a high speed VLSI chip for JPEG image compression standard.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Systolic algorithms for tree pattern matching.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

A VLSI Architecture for Computer the Tree-to-Tree Distance.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

A systolic algorithm and architecture for image thinning.

[BibT_eX]

[DOI]

K. B. Doreswamy

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

A prototype VLSI chip architecture for JPEG image compression.

[BibT_eX]

[DOI]

Martin Zagar

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Efficient computation of gabor filter based multiresolution responses.

[BibT_eX]

[DOI]

Pattern Recognit., 1994

VLSI Architectures for Pattern Matching.

[BibT_eX]

[DOI]

Int. J. Pattern Recognit. Artif. Intell., 1994

Modeling Sensor Confidence for Sensor Integration Tasks.

[BibT_eX]

[DOI]

Int. J. Pattern Recognit. Artif. Intell., 1994

ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

A Parallel Algorithm and Architecture for Robot Path Planning.

[BibT_eX]

[DOI]

Bharadwaj Parthasarathy

Proceedings of the 8th International Symposium on Parallel Processing, 1994

An efficient VLSI architecture for template matching based on moment preserving pattern matching.

[BibT_eX]

[DOI]

Satish Venugopal

Proceedings of the 12th IAPR International Conference on Pattern Recognition, 1994

An Efficient VLSI Architecture for Template Matching.

[BibT_eX]

[DOI]

Satish Venugopal

Proceedings of the 1994 International Conference on Parallel Processing, 1994

A VLSI Chip for Template Matching.

[BibT_eX]

[DOI]

Satish Venugopal

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993

VLSI architectures for polygon recognition.

[BibT_eX]

[DOI]

Horst Bunke

IEEE Trans. Very Large Scale Integr. Syst., 1993

MARVLE: a VLSI chip for data compression using tree-based codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1993

SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm.

[BibT_eX]

[DOI]

M. Varanasi

IEEE Trans. Very Large Scale Integr. Syst., 1993

Hardware Algorithms for Polygon Matching.

[BibT_eX]

[DOI]

Horst Bunke

Proceedings of the Sixth International Conference on VLSI Design, 1993

SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division.

[BibT_eX]

[DOI]

M. Varanasi

Proceedings of the Sixth International Conference on VLSI Design, 1993

VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis.

[BibT_eX]

[DOI]

Ramesh C. Jain

Proceedings of the Seventh International Parallel Processing Symposium, 1993

A Model for Determining Sensor Confidence.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993

A Systolic Array for Approximate String Matching.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

SMAC: A Scene Matching Chip.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992

Gabor filter-based edge detection.

[BibT_eX]

[DOI]

Pattern Recognit., 1992

A VLSI systolic array processor chip for computing joins in a relational database.

[BibT_eX]

[DOI]

K. R. Balaji

Hassan N. Srinidhi

Microprocess. Microsystems, 1992

A Two-dimensional Systolic Array Processor for Image Processing.

[BibT_eX]

[DOI]

Patrick McCabe

Proceedings of the Fifth International Conference on VLSI Design, 1992

A CMOS VLSI Chip for Motion Detection.

[BibT_eX]

[DOI]

S. Kurji

Proceedings of the Fifth International Conference on VLSI Design, 1992

trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations.

[BibT_eX]

[DOI]

Alade Tokuta

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 1992

A Systolic Algorithm and Architecture for Galois Field Arithmetic.

[BibT_eX]

[DOI]

M. Varanasi

Proceedings of the 6th International Parallel Processing Symposium, 1992

A VLSI architecture for hierarchical scene matching.

[BibT_eX]

[DOI]

R. Venkatesan

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

A VLSI hardware accelerator for dynamic time warping.

[BibT_eX]

[DOI]

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

SIBA: a VLSI systolic array chip for image processing.

[BibT_eX]

[DOI]

Patrick McCabe

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

Edge detection models based on Gabor filters.

[BibT_eX]

[DOI]

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992

MARVLE: A VLSI Chip for Variable Length Encoding and Decoding.

[BibT_eX]

[DOI]

Jeffrey W. Flieder

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

A VLSI architecture for a half-edge-based corner detector.

[BibT_eX]

[DOI]

Sanjay Nichani

Mach. Vis. Appl., 1991

A VLSI architecture for dynamic scene analysis.

[BibT_eX]

[DOI]

CVGIP Image Underst., 1991

An architecture to implement multiresolution.

[BibT_eX]

[DOI]

Proceedings of the 1991 International Conference on Acoustics, 1991

1990

Corner detection.

[BibT_eX]

[DOI]

Sanjay Nichani

Pattern Recognit., 1990

A parallel architecture for data compression.

[BibT_eX]

[DOI]

Selwyn Henriques

Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

Effect of Data Compression Hardware on the Performance of a Relational Database Machine.

[BibT_eX]

[DOI]

Hassan N. Srinidhi

Proceedings of the First International Conference on Databases, 1990

A VLSI architecture for difference picture-based dynamic scene analysis.

[BibT_eX]

[DOI]

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

Fast spatiotemporal filters.

[BibT_eX]

[DOI]

K. R. Namaduri

Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

SAP: design of a systolic array processor for computation in vision.

[BibT_eX]

[DOI]

Sanjay Nichani

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

Enhancing arithmetic and tree-based coding.

[BibT_eX]

[DOI]

Inf. Process. Manag., 1989

A VLSI system for difference picture-based motion analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Tools for Artificial Intelligence: Architectures, 1989

On Software and Hardware Techniques of Data Engineering.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Data Engineering, 1989

Adaptive and pipelined VLSI designs for tree-based codes.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988

A VLSI architecture for computing scale space.

[BibT_eX]

[DOI]

Mubarak Shah

Comput. Vis. Graph. Image Process., 1988

Software and Hardware Enhancement of Arithmetic Coding.

[BibT_eX]

[DOI]

Proceedings of the Statistical and Scientific Database Management, 1988

A scheme for data compression in supercomputers.

[BibT_eX]

[DOI]