Myung-Jun Choe

According to our database, Myung-Jun Choe authored at least 12 papers between 1999 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR.

Lucas Duncan, Brian Dupaix, Jamin J. McCue, Brandon Mathieu, Matthew LaRue, Vipul J. Patel, Mesfin Teshome, Myung-Jun Choe, Waleed Khalil

IEEE J. Solid State Circuits, 2017

16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR.

Lucas Duncan, Brian Dupaix, Jamin J. McCue, Brandon Mathieu, Matthew LaRue, Mesfin Teshome, Myung-Jun Choe, Waleed Khalil

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2005

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation.

Myung-Jun Choe, Kwang-Hyun Baek, Mesfin Teshome

IEEE J. Solid State Circuits, 2005

Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.

Bo Hu, Zhao Li, Lili Zhou, Chuanjin Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters.

Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.

Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers.

Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002

A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance.

Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

High-Speed, Low-Spurious CMOS Analog -to -Digital Converter

Myung-Jun Choe

PhD thesis, 2001

An 8-b 100-MSample/s CMOS pipelined folding ADC.

Myung-Jun Choe, Bang-Sup Song, Kantilal Bacrania

IEEE J. Solid State Circuits, 2001

2000

A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming.

Myung-Jun Choe, Bang-Sup Song, Kantilal Bacrania

IEEE J. Solid State Circuits, 2000

1999

A 5-MHz IF digital FM demodulator.

Jaejin Park, Eurho Joe, Myung-Jun Choe, Bang-Sup Song

IEEE J. Solid State Circuits, 1999