Myung Hoon Sunwoo

Orcid: 0000-0001-6412-5185

According to our database1, Myung Hoon Sunwoo authored at least 127 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to multimedia and communications".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
An Automated Cardiac Arrhythmia Classification Network for 45 Arrhythmia Classes Using 12-Lead Electrocardiogram.
IEEE Access, 2024

Efficient Deep Retinal Fundus Image-Based Network for Alzheimer's Disease Diagnosis Using Mobile Device Applications.
IEEE Access, 2024

2023
Area-Efficient Intellectual Property (IP) Design of Advanced Encryption Standard.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

A Low-Complexity Sorting Network for a Fast List Polar Decoder.
IEEE Access, 2023

Hardware Architecture for Reducing Worst-Case Latency in Fast SCF Polar Decoders.
IEEE Access, 2023

2022
Multilevel Feature Extraction Using Wavelet Attention for Deep Joint Demosaicking and Denoising.
IEEE Access, 2022

DNN-based Cancer Recurrence Predictor using FPGA.
Proceedings of the 19th International SoC Design Conference, 2022

Resource-Efficient FPGA Implementation of Advanced Encryption Standard.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Deep Learning aided BP-Flip Decoding of Polar Codes.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Live Demonstration: Efficient Deep Learning Algorithm for Alzheimer's Disease Diagnosis using Retinal Images.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Efficient Deep Learning Algorithm for Alzheimer's Disease Diagnosis using Retinal Images.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Fast Multibit Decision Polar Decoder for Successive-Cancellation List Decoding.
J. Signal Process. Syst., 2021

10.07uW Multi-Mode Baseband Transceiver for Encrypted Capsule Endoscopy.
J. Signal Process. Syst., 2021

HDR Image Reconstruction Using Segmented Image Learning.
IEEE Access, 2021

Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder.
Proceedings of the 18th International SoC Design Conference, 2021

Implementation of CNN based Demosaicking on FPGA.
Proceedings of the 18th International SoC Design Conference, 2021

A Uniformly Segmented SC-Flip Decoder for Polar Codes with Memory Reduction Methods.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Multi-Channel Input Deep Convolutional Neural Network for Mammogram Diagnosis.
Proceedings of the International SoC Design Conference, 2020

2019
Low-Complexity High-Throughput Bit-Wise LDPC Decoder.
J. Signal Process. Syst., 2019

Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT).
J. Signal Process. Syst., 2019

A Fast Mode Decision Algorithm Using Hierarchical and Skip Methods for Intra Prediction in HEVC.
J. Signal Process. Syst., 2019

Adaptive Early Termination Algorithm Using Coding Unit Depth History in HEVC.
J. Signal Process. Syst., 2019

CASA: A Convolution Accelerator using Skip Algorithm for Deep Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Fast Convolution Algorithm for Convolutional Neural Networks.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Area-Efficient Scheduling Scheme Based FFT Processor for Various OFDM Systems.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Special session: Low power LDPC deocder using adaptive forced convergence algorithm.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Low power BCH decoder using early termination scheme for WBAN standard.
Proceedings of the International SoC Design Conference, 2017

2016
Low-Complexity First-Two-Minimum-Values Generator for Bit-Serial LDPC Decoding.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Fast CU size decision method for HEVC using CU split information of adjacent frames.
Proceedings of the International SoC Design Conference, 2016

Texture-based fast CU size decision algorithm for HEVC intra coding.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Novel frame rate up-conversion algorithm based on prediction and recursive search.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Hierarchical fast mode decision algorithm for intra prediction in HEVC.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
New Frame Rate Up-Conversion Algorithms With Low Computational Complexity.
IEEE Trans. Circuits Syst. Video Technol., 2014

Design and implementation of CAN data compression algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

New parallel MDC FFT processor with efiicient scheduling scheme.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Simplified forced convergence decoding algorithm for low power LDPC decoders.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders.
J. Signal Process. Syst., 2013

MESIP: A Configurable and Data Reusable Motion Estimation Specific Instruction-Set Processor.
IEEE Trans. Circuits Syst. Video Technol., 2013

Efficient loop accelerator for Motion Estimation Specific Instruction-set Processor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

An interferer filtering CMOS LNA for multiband wireless receiver.
Proceedings of the 7th International Conference on Ubiquitous Information Management and Communication, 2013

2012
Guest Editorial - Special Issue on Signal Processing Circuits and Systems for Broadband Communications.
J. Signal Process. Syst., 2012

Erratum to: Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications.
J. Signal Process. Syst., 2012

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications.
J. Signal Process. Syst., 2012

Low complexity full parallel Multi-Split LDPC decoder reusing sign wire of row processor.
Proceedings of the International SoC Design Conference, 2012

Low complexity FFT/IFFT processor for high-speed OFDM system using efficient multiplier scheduling.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Flexible IME instruction and its architecture for various fast ME algorithms.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Data reusable search scan methods for low power motion estimation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Efficient computation reduction algorithms for frame rate up-conversion.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Phase recovery for QPSK transmission without using complex multipliers.
Proceedings of the 6th International Conference on Ubiquitous Information Management and Communication, 2012

Simplified Frame Rate Up-conversion algorithm with low computational complexity.
Proceedings of the 20th European Signal Processing Conference, 2012

2011
Efficient program control schemes for Motion Estimation specific processor.
Proceedings of the International SoC Design Conference, 2011

High-speed and low complexity carrier recovery for DP-QPSK transmission.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

High speed eight-parallel mixed-radix FFT Processor for OFDM systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Novel fractional motion estimation algorithm and architecture using Sub-block Combination.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Integer-pel Motion Estimation specific instructions and their hardware architecture for ASIP.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Low complexity soft-decision demapper for DVB-S2 using phase selection method.
Proceedings of the 5th International Conference on Ubiquitous Information Management and Communication, 2011

2010
Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet.
J. Signal Process. Syst., 2010

An efficient skipping method of H.264/AVC weighted prediction for various illuminating effects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

High-speed architecture for three-parallel Reed-Solomon decoder using S-DCME.
Proceedings of the 4th International Conference on Ubiquitous Information Management and Communication, 2010

Power efficient column operation-based message-passing schedule for regular ldpc decoder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Sub-block combination fractional motion estimation algorithms for H.264/AVC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Low Power Complexity-Reduced ME and Interpolation Algorithms for H.264/AVC.
J. Signal Process. Syst., 2009

Multi-level modulation soft-decision demapper for DVB-S2.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Efficient Synchronizer Architecture using Common Autocorrelator for DVB-S2.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Simplified sum-product algorithm using piecewise linear function approximation for low complexity LDPC decoding.
Proceedings of the 3rd International Conference on Ubiquitous Information Management and Communication, 2009

Novel residual prediction scheme for hybrid video coding.
Proceedings of the International Conference on Image Processing, 2009

Low complexity synchronizer architecture based on common autocorrelator for Digital Video Broadcasting system.
Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Novel frame selection methods for multi-reference motion estimation.
Proceedings of the 16th International Conference on Digital Signal Processing, 2009

2008
ASIP Approach for Implementation of H.264/AVC.
J. Signal Process. Syst., 2008

SPOCS: Application Specific Signal Processor for OFDM Communication Systems.
J. Signal Process. Syst., 2008

New simplified sum-product algorithm for low complexity LDPC decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Fast multiple reference frame selection methods for H.264/AVC.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Efficient coarse frequency synchronizer using serial correlator for DVB-S2.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Data-aided algorithm based frequency synchronizer for DVB-S2.
Proceedings of the 2nd International Conference on Ubiquitous Information Management and Communication, 2008

Efficient frame selection schemes for multi-reference and variable block size Motion Estimation.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Novel fractional pixel motion estimation algorithm using motion prediction and fast search pattern.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Hardware efficient frequency estimator based on data-aided algorithm for digital video broadcasting system.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
An Efficient Data-Aided Initial Frequency Synchronizer for DVB-S2.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

AN ASIP Approach for H.264/AVC Implementation Having Novel Coprocessors.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Low Power ASIP Architecture Optimization based on Target Application Profiling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Novel Non-linear Inverse Quantization Algorithm and its Architecture for Digital Audio Codecs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Simplified Degree Computationless Modified Euclid's Algorithm and its Architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Efficient DSP Architecture for Viterbi Decoding with Small Trace Back Latency.
IEICE Trans. Commun., 2006

VSIP : Video Specific Instruction Set Processor for H.264/AVC.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Enhanced degree computationless modified Euclid's algorithm for Reed-Solomon decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

ASIP approach for implementation of H.264/AVC.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Enhanced Degree Computationless Modified Euclid's Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

VSIP : Implementation of Video Specific Instruction-set Processor.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Guest Editorial.
J. VLSI Signal Process., 2005

Implementation of a Wireless Multimedia DSP Chip for Mobile Applications.
J. VLSI Signal Process., 2005

New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor.
EURASIP J. Adv. Signal Process., 2005

Efficient DSP architecture for high-quality audio algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Novel instructions and their hardware architecture for video signal processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Novel digital signal processing unit for Ethernet receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A Multiplierless 2-D Convolver Chip for Real-Time Image Processing.
J. VLSI Signal Process., 2004

A multislot-interleaved turbo-coded MC-CDMA/TDD uplink system with pre-equalization using polynomial fitting and extension for uplink channel estimation.
Proceedings of the IEEE 15th International Symposium on Personal, 2004

Implementation of application-specific DSP for OFDM systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Novel bit manipulation unit for communication digital signal processors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT.
J. VLSI Signal Process., 2003

Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs.
EURASIP J. Adv. Signal Process., 2003

A high-speed blind DFE equalizer using an error feedback filter for QAM modems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A continuous flow mixed-radix FFT architecture with an in-place algorithm.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Application-Specific DSP Architecture For Fast Fourier Transform.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Implementation factors of the multi-rate parallel interference canceller for the IMT-2000 3GPP system.
Proceedings of the 55th IEEE Vehicular Technology Conference, 2002

A new turbo-coded OFDM system using orthogonal code multiplexing.
Proceedings of the 55th IEEE Vehicular Technology Conference, 2002

A high-speed FFT processor for OFDM systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of a high-speed Reed-Solomon decoder.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A low power and area efficient FIR filter chip for PRML read channels.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
A MDSP (multimedia DSP) chip for portable multimedia applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A low complexity Reed-Solomon architecture using the Euclid's algorithm.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Implementation of a Sliding Memory Plane Image Processor.
J. Parallel Distributed Comput., 1998

An Efficient Variable-Length Tap FIR Filter Chip.
Proceedings of the ASP-DAC '98, 1998

An Effcient 2-D Convolver Chip for Real Time Image Processing.
Proceedings of the ASP-DAC '98, 1998

1997
SliM-II: A Linear Array SIMD Processor for Real-time Image Processing.
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

A Linear Array Parallel Image Processor: SliM-II.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Implementation of a SliM Array Processor.
Proceedings of IPPS '96, 1996

1995
Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1993
A Sliding Memory Plane Array Processor.
IEEE Trans. Parallel Distributed Syst., 1993

1992
A flexibility coupled hypercube multiprocessor for high level vision.
Mach. Vis. Appl., 1992

1990
Flexibly Coupled Multiprocessors for Image Processing.
J. Parallel Distributed Comput., 1990

Vista for a general purpose computer vision system.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990

A sliding memory array processor for low level vision.
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990


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