Myoungjun Lee

Orcid: 0000-0001-9774-5276

According to our database1, Myoungjun Lee authored at least 3 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Time-sensitivity-aware shared cache architecture for multi-core embedded systems.
J. Supercomput., 2019

MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems.
ACM Trans. Archit. Code Optim., 2019

2013
Performance-controllable shared cache architecture for multi-core soft real-time systems.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013


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