Myounggon Kang
Orcid: 0000-0003-4132-0038
According to our database1,
Myounggon Kang
authored at least 12 papers
between 2008 and 2024.
Collaborative distances:
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Bibliography
2024
Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning.
IEEE Access, 2024
2023
Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET).
IEEE Access, 2023
2020
A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems.
Sensors, 2020
2017
Characterization of oxide trap density with the charge pumping technique in dual-layer gate oxide.
IEICE Electron. Express, 2017
Investigation of capture and emission dependence between individual traps from complex random telegraph signal noise analysis.
IEICE Electron. Express, 2017
2011
Microelectron. J., 2011
2010
Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2010
IEICE Trans. Electron., 2010
A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory.
IEICE Trans. Electron., 2010
2009
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure.
IEEE J. Solid State Circuits, 2009
2008
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.
IEEE J. Solid State Circuits, 2008
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008