Myeong-Eun Hwang

According to our database, Myeong-Eun Hwang authored at least 8 papers between 2004 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

DPFFs: C²MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling.

Myeong-Eun Hwang, Sungoh Kwon

J. Electr. Comput. Eng., 2016

2010

ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling.

Myeong-Eun Hwang, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.

Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology.

Myeong-Eun Hwang, Kaushik Roy

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.

Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.

Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005

Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies.

Myeong-Eun Hwang, Arijit Raychowdhury, Kairshik Roy

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004

Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies.

Myeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004