Muya Chang
Orcid: 0000-0002-3035-1106Affiliations:
- Purdue University, West Lafayette, IN, USA
- Georgia Institute of Technology, Atlanta, GA, USA (PhD 2020)
According to our database1,
Muya Chang
authored at least 32 papers
between 2018 and 2024.
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Bibliography
2024
In-Situ Privacy via Mixed-Signal Perturbation and Hardware-Secure Data Reversibility.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking.
IEEE J. Solid State Circuits, January, 2024
IEEE Trans. Pattern Anal. Mach. Intell., 2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 24/48V to 0.8V-1.2V All-Digital Synchronous Buck Converter with Package-Integrated GaN power FETs and 180nm Silicon Controller IC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
A 2.38 MCells/mm<sup>2</sup> 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding.
IEEE J. Solid State Circuits, 2022
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection.
IEEE J. Solid State Circuits, 2022
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller.
IEEE J. Solid State Circuits, 2022
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm<sup>2</sup>RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
An Analog Clock-free Compute Fabric base on Continuous-Time Dynamical System for Solving Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A 65nm Thermometer-Encoded Time/Charge-Based Compute-in-Memory Neural Network Accelerator at 0.735pJ/MAC and 0.41pJ/Update.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing.
IEEE J. Solid State Circuits, 2021
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers.
IEEE J. Solid State Circuits, 2020
A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics.
IEEE J. Solid State Circuits, 2020
A 65nm Image Processing SoC Supporting Multiple DNN Models and Real-Time Computation-Communication Trade-Off Via Actor-Critical Neuro-Controller.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 65nm 1.1-to-9.1TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Model-Based and Model-Free Swarm Robotics.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Efficient Signal Reconstruction via Distributed Least Square Optimization on a Systolic FPGA Architecture.
Proceedings of the IEEE International Conference on Acoustics, 2019
Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations.
Proceedings of the 76th Device Research Conference, 2018