Mursina Khatun

According to our database, Mursina Khatun authored at least 3 papers in 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS.

Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

A 2⁷-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS.

Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS.

Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024