Murilo R. Perleberg

Orcid: 0000-0002-1398-5342

According to our database1, Murilo R. Perleberg authored at least 19 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Memory-Centered Motion Estimation System With CTB-Based Full-Splitting Algorithm.
IEEE Trans. Consumer Electron., May, 2024

A Real-Time UHD 4K Hardware for VVC Affine Linear Equation System Solving.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

Coding Efficiency and Time Evaluation of Apple A15 Bionic Chipset HEVC Encoder.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical Flow.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

4K UHD@60fps Design For The VVC Affine Motion Estimation Reconstructor.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Hardware Design for the Affine Motion Compensation of the VVC Standard.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

Efficient Architecture for VVC Angular Intra Prediction based on a Hardware-Friendly Heuristic.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

Efficient Hardware Design for the VVC Affine Motion Compensation Exploiting Multiple Constant Multiplication.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022
Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction.
J. Real Time Image Process., 2022

2021
Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing.
J. Real Time Image Process., 2021

2020
6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
IEEE Des. Test, 2020

A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Enhancing Real-Time Motion Estimation through Approximate High-Level Synthesis.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019
Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy.
IEEE Trans. Circuits Syst. Video Technol., 2019

2018
A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

ASIC power-estimation accuracy evaluation: A case study using video-coding architectures.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


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