Murari Mani

According to our database, Murari Mani authored at least 8 papers between 2004 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Large-scale multi-corner leakage optimization under the sign-off timing environment.

George Gonzalez, Murari Mani, Mahesh Sharma

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2007

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits.

Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.

Murari Mani, Ashish Kumar Singh, Michael Orshansky

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Application of fast SOCP based statistical sizing in the microprocessor design flow.

Murari Mani, Mahesh Sharma, Michael Orshansky

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.

Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky

Proceedings of the 43rd Design Automation Conference, 2006

2005

Statistical technology mapping for parametric yield.

Ashish Kumar Singh, Murari Mani, Michael Orshansky

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An efficient algorithm for statistical minimization of total power under timing yield constraints.

Murari Mani, Anirudh Devgan, Michael Orshansky

Proceedings of the 42nd Design Automation Conference, 2005

2004

A New Statistical Optimization Algorithm for Gate Sizing.

Murari Mani, Michael Orshansky

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004