Muralidhar Pullakandam

According to our database, Muralidhar Pullakandam authored at least 12 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2025

FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

J. Supercomput., February, 2025

2024

High-Speed Power Allocation in NOMA System Using FPGA-Based DNN.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

J. Circuits Syst. Comput., September, 2024

Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

Int. J. Circuit Theory Appl., September, 2024

2023

A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

Des. Autom. Embed. Syst., September, 2023

SoC-based real-time SVM classification with integrated training using HLS and PYNQ.

B. B. Shabarinath, Muralidhar Pullakandam

Microprocess. Microsystems, 2023

Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU.

Sujay Kumar Mandal, Muralidhar Pullakandam, Rama Muni Reddy Yanamala

Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

Advanced Powerplanning Strategy Utilising Aprisa - Image Edge Detector.

Roshan Agarwal, Muralidhar Pullakandam, Gopinath Agrahara, Amarnadh Akavarapu

Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022

An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

The chaotic-based challenge feed mechanism for Arbiter Physical Unclonable Functions (APUFs) with enhanced reliability in IoT security.

Raveendra Podeti, Sreehari Rao Patri, Muralidhar Pullakandam

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Efficient successive cancellation decoder architecture for multi-kernel polar codes.

Nandini Jali, Muralidhar Pullakandam, Sreehari Rao Patri

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021

Highly reliable XoR Feed Arbiter Physical Unclonable Function (XFAPUF) in 180 nm process for IoT security.

Raveendra Podeti, Sreehari Rao Patri, Muralidhar Pullakandam

Microprocess. Microsystems, November, 2021

ReOPUF: Relaxation Oscillator Physical Unclonable Function for Reliable Key Generation in IoT Security.

Raveendra Podeti, Srihari Rao Patri, Srinivas Katkoori, Muralidhar Pullakandam

Proceedings of the Internet of Things. Technology and Applications, 2021