Munehiro Yoshida

According to our database, Munehiro Yoshida authored at least 5 papers between 1989 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

Performance Evaluation of Compiler Controlled Power Saving Scheme.

Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

1997

Flexible test mode approach for 256-Mb DRAM.

Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik

IEEE J. Solid State Circuits, 1997

1996

A 286 mm² 256 Mb DRAM with ×32 both-ends DQ.

Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii

IEEE J. Solid State Circuits, 1996

Fault-tolerant designs for 256 Mb DRAM.

Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao

IEEE J. Solid State Circuits, 1996

1989

A 45-ns 16-Mbit DRAM with triple-well structure.

Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita

IEEE J. Solid State Circuits, October, 1989