Muhannad S. Bakir
Affiliations:- Georgia Institute of Technology, Atlanta GA, USA
According to our database1,
Muhannad S. Bakir
authored at least 32 papers
between 2002 and 2024.
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Bibliography
2024
Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
2022
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Integrated Silicon Microfluidic Cooling of a High-Power Overclocked CPU for Efficient Thermal Management.
IEEE Access, 2022
High-performance Flexible Microelectrode Array with PEDOT: PSS Coated 3D Micro-cones for Electromyographic Recording.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
2021
Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021
2020
CoRR, 2020
Proceedings of the VLSI-SoC: Design Trends, 2020
A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
2019
High Density and Low-Temperature Interconnection Enabled by Mechanical Self-Alignment and Electroless Plating.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
Towards a 1.1 mm<sup>2</sup> free-floating wireless implantable neural recording SoC.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Microfabrication, assembly, and hermetic packaging of mm-sized free-floating neural probes.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Design considerations for 2.5-D and 3-D integration accounting for thermal constraints.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
The impact of 3D stacking on GPU-accelerated deep neural networks: An experimental study.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Fabrication of and cell growth on 'silicon membranes' with high density TSVs for bio-sensing applications.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer.
Proceedings of the IEEE 25th International SOC Conference, 2012
2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
2004
Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
2002
Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002