Muhammed Bolatkale

Orcid: 0000-0001-9608-2036

According to our database1, Muhammed Bolatkale authored at least 23 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme.
IEEE J. Solid State Circuits, April, 2024

2023
A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS.
IEEE J. Solid State Circuits, 2022

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction.
IEEE J. Solid State Circuits, 2022

A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth.
IEEE J. Solid State Circuits, 2016

15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2011
A Single-Temperature Trimming Technique for MOS-Input Operational Amplifiers Achieving 0.33 μ V/°C Offset Drift.
IEEE J. Solid State Circuits, 2011

A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW.
IEEE J. Solid State Circuits, 2011

A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008
A BiCMOS Operational Amplifier Achieving 0.33μV°C Offset Drift using Room-Temperature Trimming.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008


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