Muhammad Yasir Qadri

According to our database1, Muhammad Yasir Qadri authored at least 25 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
FPGA Based Intelligent Hardware Trojan Design and its SoC Implementation.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2021
GA-EDA: Hybrid Design Space Exploration Engine for Multicore Architecture.
J. Circuits Syst. Comput., 2021

2020
An Integer Cat Swarm Optimization Approach for Energy and Throughput Efficient MPSoC Design.
Int. J. Comput. Intell. Syst., 2020

Estimation of distribution-based multiobjective design space exploration for energy and throughput-optimized MPSoCs.
Turkish J. Electr. Eng. Comput. Sci., 2020

2019
SWT and PCA image fusion methods for multi-modal imagery.
Multim. Tools Appl., 2019

Analytical models of Energy and Throughput for Caches in MPSoCs.
CoRR, 2019

Scalable, energy-aware system modeling and application-specific reconfiguration of MPSocs with a type-2 fuzzy logic system.
Comput. Electr. Eng., 2019

2018
AC-DSE: Approximate Computing for the Design Space Exploration of Reconfigurable MPSoCs.
J. Circuits Syst. Comput., 2018

Optimizing energy and throughput for MPSoCs: an integer particle swarm optimization approach.
Computing, 2018

2017
Energy-efficient data prefetch buffering for low-end embedded processors.
Microelectron. J., 2017

Energy-efficient MAC protocols for wireless BANs: comparison, classification, applications and challenges.
Int. J. Sens. Networks, 2017

NSGA-II-Based Design Space Exploration for Energy and Throughput Aware Multicore Architectures.
Cybern. Syst., 2017

2016
Fuzzy logic based energy and throughput aware design space exploration for MPSoCs.
Microprocess. Microsystems, 2016

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures.
J. Circuits Syst. Comput., 2016

Ant Colony Optimization for multicore re-configurable architecture.
AI Commun., 2016

Architectural Enhancement of LEON3 Processor for Real Time and Feedback Applications.
Proceedings of the International Conference on Frontiers of Information Technology, 2016

2015
Software-Controlled Instruction Prefetch Buffering for Low-End Processors.
J. Circuits Syst. Comput., 2015

2014
Energy and throughput aware fuzzy logic based reconfiguration for MPSoCs.
J. Intell. Fuzzy Syst., 2014

Hardware realization of locally normalized cross correlation algorithm.
Proceedings of the 2nd International Conference on Systems and Informatics, 2014

2010
Analytical Evaluation of Energy and Throughput for Multilevel Caches.
Proceedings of the 12th UKSim, 2010

A Fuzzy Logic Reconfiguration Engine for Symmetric Chip Multiprocessors.
Proceedings of the CISIS 2010, 2010

JetBench: An Open Source Real-time Multiprocessor Benchmark.
Proceedings of the Architecture of Computing Systems, 2010

A fuzzy logic based dynamic reconfiguration scheme for optimal energy and throughput in symmetric chip multiprocessors.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
Low Power Processor Architectures and Contemporary Techniques for Power Optimization - A Review.
J. Comput., 2009

Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors.
EURASIP J. Embed. Syst., 2009


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