Muhammad Waqar Azhar

Orcid: 0000-0003-0477-4540

According to our database1, Muhammad Waqar Azhar authored at least 18 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
An Efficient Hybrid Deep Learning Accelerator for Compact and Heterogeneous CNNs.
ACM Trans. Archit. Code Optim., June, 2024

Simulation of Quantum Computers: Review and Acceleration Opportunities.
CoRR, 2024

Fusing Depthwise and Pointwise Convolutions for Efficient Inference on GPUs.
Proceedings of the Workshop Proceedings of the 53rd International Conference on Parallel Processing, 2024

Scratchpad Memory Management for Deep Learning Accelerators.
Proceedings of the 53rd International Conference on Parallel Processing, 2024

DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints.
ACM Trans. Archit. Code Optim., September, 2023

Exploiting the Potential of Flexible Processing Units.
Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023

RAINBOW: Multi-Dimensional Hardware-Software Co-Design for DL Accelerator On-Chip Memory.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Evaluation of heterogeneous AIoT Accelerators within VEDLIoT.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023


ARADA: Adaptive Resource Allocation for Improving Energy Efficiency in Deep Learning Accelerators.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints.
ACM Trans. Archit. Code Optim., 2022

FiBHA: Fixed Budget Hybrid CNN Accelerator.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

VSA: A Hybrid Vector-Systolic Architecture.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2019
SaC: Exploiting Execution-Time Slack to Save Energy in Heterogeneous Multicore Systems.
Proceedings of the 48th International Conference on Parallel Processing, 2019

2017
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures.
ACM Trans. Archit. Code Optim., 2017

2012
Viterbi Accelerator for Embedded Processor Datapaths.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2010
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010


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