Muhammad N. Marsono

Orcid: 0000-0002-7468-7461

According to our database1, Muhammad N. Marsono authored at least 79 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Elephant flow detection intelligence for software-defined networks: a survey on current techniques and future direction.
Evol. Intell., August, 2024

Improved Feature Selection and Stream Traffic Classification Based on Machine Learning in Software-Defined Networks.
IEEE Access, 2024

iCuSMAT-DT: A Two-Tier Detection Mechanism for High-Rate DDoS Attacks and Discriminating Benign Flash Traffic in Software-Defined Networks.
Proceedings of the International Conference on Smart Applications, 2024

2023
Motion Pattern-Based Scene Classification Using Adaptive Synthetic Oversampling and Fully Connected Deep Neural Network.
IEEE Access, 2023

3D-DNaPE: Dynamic Neighbor-Aware Performance Enhancement for Thermally Constrained 3D Many-Core Systems.
IEEE Access, 2023

A Two-Tier Anomaly-based Intrusion Detection Approach for IoT-Enabled Smart Cities.
Proceedings of the IEEE INFOCOM 2023, 2023

2022
RtFog: A Real-Time FPGA-Based Fog Node With Remote Dynamically Reconfigurable Application Plane for Fog Analytics Redeployment.
IEEE Trans. Green Commun. Netw., 2022

An FPGA-based IP Core Subscription-Oriented Fog Computing Platform.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Traffic Classification based on Incremental Learning Algorithms for the Software-Defined Networks.
Proceedings of the International Conference on Frontiers of Information Technology, 2022

2021
Collaborative detection and mitigation of DDoS in software-defined networks.
J. Supercomput., 2021

A comprehensive survey of load balancing techniques in software-defined network.
J. Netw. Comput. Appl., 2021

DPLBAnt: Improved load balancing technique based on detection and rerouting of elephant flows in software-defined networks.
Comput. Commun., 2021

Software-defined networks for resource allocation in cloud computing: A survey.
Comput. Networks, 2021

PEW: Prediction-Based Early Dark Cores Wake-up Using Online Ridge Regression for Many-Core Systems.
IEEE Access, 2021

An FPGA-based Middlebox with Remote Dynamically Reconfigurable Application Plane.
Proceedings of the IEEE Region 10 Conference, 2021

Early Flow Table Eviction Impact on Delay and Throughput in Software-Defined Networks.
Proceedings of the 11th IEEE International Conference on Control System, 2021

A Centralized Token-based Medium Access Control Mechanism for Wireless Network-on-Chip.
Proceedings of the International Conference on Artificial Intelligence and Computer Science Technology, 2021

2020
Collaborative Detection and Mitigation of Distributed Denial-of-Service Attacks on Software-Defined Network.
Mob. Networks Appl., 2020

Edge Computing Intelligence Using Robust Feature Selection for Network Traffic Classification in Internet-of-Things.
IEEE Access, 2020

Flow-Aware Elephant Flow Detection for Software-Defined Networks.
IEEE Access, 2020

2019
Interleaved Incremental/Decremental Support Vector Machine for Embedded System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Improved quantum circuit modelling based on Heisenberg representation.
Quantum Inf. Process., 2018

A linked list run-length-based single-pass connected component analysis for real-time embedded hardware.
J. Real Time Image Process., 2018

drDRM: A PUF-Based Dynamically Reconfigurable DRM Mechanism for FPGA-Based Platform.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

First Line Defense Against Spreading New Malware in the Network.
Proceedings of the 2018 10th Computer Science and Electronic Engineering Conference, 2018

2017
Ping-lock round robin arbiter.
Microelectron. J., 2017

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform.
Microprocess. Microsystems, 2017

Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms.
J. Syst. Archit., 2017

hpFog: A FPGA-Based Fog Computing Platform.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

2016
FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application.
Int. J. Reconfigurable Comput., 2016

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture.
Int. J. Reconfigurable Comput., 2016

Online network traffic classification with incremental learning.
Evol. Syst., 2016

Online Incremental Learning for High Bandwidth Network Traffic Classification.
Appl. Comput. Intell. Soft Comput., 2016

Improved Flow Control for Minimal Fully Adaptive Routing in 2D Mesh NoC.
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016

A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015
2-D DWT System Architecture for Image Compression.
J. Signal Process. Syst., 2015

Automated Dataset Generation for Training Peer-to-Peer Machine Learning Classifiers.
J. Netw. Syst. Manag., 2015

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique.
Int. J. Reconfigurable Comput., 2015

Incorporating known malware signatures to classify new malware variants in network traffic.
Int. J. Netw. Manag., 2015

Built-in Self Test Power and Test Time Analysis in On-chip Networks.
Circuits Syst. Signal Process., 2015

Hardware/software partitioning of embedded System-on-Chip applications.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

rrBox: A remote dynamically reconfigurable network processing middlebox.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

A closed loop transmitting power self-calibration scheme for energy efficient WiNoC architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Online data stream classification with incremental semi-supervised learning.
Proceedings of the Second ACM IKDD Conference on Data Sciences, 2015

2014
Hardware implementation of evolvable block-based neural networks utilizing a cost efficient sigmoid-like activation function.
Neurocomputing, 2014

Optimization of structure and system latency in evolvable block-based neural networks using genetic algorithm.
Neurocomputing, 2014

Malware detection using augmented naive Bayes with domain knowledge and under presence of class noise.
Int. J. Inf. Comput. Secur., 2014

Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip.
Appl. Comput. Intell. Soft Comput., 2014

Stateless Malware Packet Detection by Incorporating Naive Bayes with Known Malware Signatures.
Appl. Comput. Intell. Soft Comput., 2014

FPGA-based quantum circuit emulation: A case study on Quantum Fourier transform.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

rrBox: Remote dynamically reconfigurable middlebox using NetFPGA.
Proceedings of the 14th International Symposium on Communications and Information Technologies, 2014

Remote dynamically reconfigurable platform using NetFPGA.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Hardware transactional memory on multi-processor FPGA platform.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Packet logging mechanism for adaptive online fault detection on Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Closed Loop Control based Power Manager for WiNoC Architectures.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

rrBox: A Remote Dynamically Reconfigurable Middlebox for Network Protection.
Proceedings of the Second International Symposium on Computing and Networking, 2014

2013
A Semi-Analytical Approach to Study the Energy Consumption of On-Chip Networks Testing.
J. Low Power Electron., 2013

Biometric encryption based on a fuzzy vault scheme with a fast chaff generation algorithm.
Future Gener. Comput. Syst., 2013

HW/SW co-design of reconfigurable hardware-based genetic algorithm in FPGAs applicable to a variety of problems.
Computing, 2013

Online NetFPGA decision tree statistical traffic classifier.
Comput. Commun., 2013

Feasible transition path generation for EFSM-based system testing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Network partitioning and GA heuristic crossover for NoC application mapping.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Selection of On-line Features for Peer-to-Peer Network Traffic Classification.
Proceedings of the Recent Advances in Intelligent Informatics, 2013

Co-simulation methodology for improved design and verification of hardware neural networks.
Proceedings of the IECON 2013, 2013

2012
Packet-level open-digest fingerprinting for spam detection on middleboxes.
Int. J. Netw. Manag., 2012

Retraining Mechanism for On-Line Peer-to-Peer Traffic Classification.
Proceedings of the Intelligent Informatics, 2012

Parameterizable Decision Tree Classifier on NetFPGA.
Proceedings of the Intelligent Informatics, 2012

GA-based parameter tuning in finger-vein biometric embedded systems for information security.
Proceedings of the 2012 1st IEEE International Conference on Communications in China (ICCC), 2012

2011
Network Worm Propagation Model Based on a Campus Network Topology.
Proceedings of the 2011 IEEE International Conference on Internet of Things (iThings) & 4th IEEE International Conference on Cyber, 2011

A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Detecting Worms Using Data Mining Techniques: Learning in the Presence of Class Noise.
Proceedings of the Sixth International Conference on Signal-Image Technology and Internet-Based Systems, 2010

2009
A spam rejection scheme during SMTP sessions based on layer-3 e-mail classification.
J. Netw. Comput. Appl., 2009

Targeting spam control on middleboxes: Spam detection based on layer-3 e-mail content classification.
Comput. Networks, 2009

2008
Prioritized e-mail servicing to reduce non-spam delay and loss: A performance analysis.
Int. J. Netw. Manag., 2008

Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation.
IET Comput. Digit. Tech., 2008

2006
Binary LNS-based naive Bayes hardware classifier for spam control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Distributed Layer-3 E-Mail Classification for Spam Control.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006


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