Muhammad Hassan
Orcid: 0000-0002-4217-3079Affiliations:
- University of Bremen, Institute of Computer Science, Germany
According to our database1,
Muhammad Hassan
authored at least 26 papers
between 2016 and 2024.
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Bibliography
2024
ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars.
ACM Trans. Embed. Comput. Syst., November, 2024
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024
cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
PhD thesis, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2019
it Inf. Technol., 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 Forum for Specification and Design Languages, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Guided lightweight Software test qualification for IP integration using Virtual Prototypes.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016