Muhammad E. S. Elrabaa

According to our database, Muhammad E. S. Elrabaa authored at least 29 papers between 1994 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Accelerating memory and I/O intensive HPC applications using hardware compression.

Saleh Alsaleh, Muhammad E. S. Elrabaa, Aiman El-Maleh, Khaled A. Daud, Ayman Hroub, Muhamed F. Mudawar, Thierry Tonellot

J. Parallel Distributed Comput., 2024

2022

DE-ZFP: An FPGA implementation of a modified ZFP compression/decompression algorithm.

Mahmoud Habboush, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Saleh Alsaleh

Microprocess. Microsystems, April, 2022

SecSoC: A Secure System on Chip Architecture for IoT Devices.

Ayman Hroub, Muhammad E. S. Elrabaa

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021

Secure Computing Enclaves Using FPGAs.

Muhammad E. S. Elrabaa, Mohammed Alasli, Marwan H. Abu-Amara

IEEE Trans. Dependable Secur. Comput., 2021

2019

A Protection and Pay-per-use Licensing Scheme for On-cloud FPGA Circuit IPs.

Muhammad E. S. Elrabaa, Mohamed A. Al-Asli, Marwan H. Abu-Amara

ACM Trans. Reconfigurable Technol. Syst., 2019

FPGA-Based Symmetric Re-Encryption Scheme to Secure Data Processing for Cloud-Integrated Internet of Things.

Mohammed Alasli, Muhammad E. S. Elrabaa, Marwan H. Abu-Amara

IEEE Internet Things J., 2019

Cloud-Based FPGA Custom Computing Machines for Streaming Applications.

Amran Al-Aghbari, Muhammad E. S. Elrabaa

IEEE Access, 2019

2018

A platform for FPGA virtualization in clouds and data centers.

Amran Al-Aghbari, Muhammad E. S. Elrabaa

Microprocess. Microsystems, 2018

FBNoC: FPGA-based network on chip emulator for full-system architectural simulation of many-core systems.

Gamil A. Ahmed, Muhammad E. S. Elrabaa

Microprocess. Microsystems, 2018

2017

A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy.

Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Sadiq M. Sait

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations.

Muhammad E. S. Elrabaa, Ayman Hroub, Muhamed F. Mudawar, Amran Al-Aghbari, Mohammed Alasli, Ahmad Khayyat

IEEE Trans. Parallel Distributed Syst., 2017

Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations.

Ayman Hroub, Muhammad E. S. Elrabaa, Muhamed F. Mudawar, Ahmad Khayyat

ACM Trans. Archit. Code Optim., 2017

2016

A low-cost platform for the prototyping and characterization of digital circuit IPs.

Muhammad E. S. Elrabaa, Amran Al-Aghbari, Mohammed Alasli, Aiman El-Maleh, Abdelhafid Bouhraoua, Mohammad R. Alshayeb

Integr., 2016

2015

Towards a Test Definition Language for Integrated Circuits.

Mohammad R. Alshayeb, Muhammad E. S. Elrabaa, Ayman Hroub, Amran Al-Aghbari, Aiman H. El-Maleh, Abdelhafid Bouhraoua

J. Circuits Syst. Comput., 2015

2014

Buffer Engineering for modified Fat Tree NoCs for Many-Core Systems-on-Chip.

Muhammad E. S. Elrabaa, Abdelhafid Bouhraoua

J. Circuits Syst. Comput., 2014

A portable high-frequency digitally controlled oscillator (DCO).

Muhammad E. S. Elrabaa

Integr., 2014

2011

Robust Two-Phase RZ Asynchronous SoC Interconnects.

Muhammad E. S. Elrabaa

IEEE Trans. Very Large Scale Integr. Syst., 2011

A hardwired NoC infrastructure for embedded systems on FPGAs.

Muhammad E. S. Elrabaa, Abdelhafid Bouhraoua

Microprocess. Microsystems, 2011

Improved Modified Fat-Tree Topology Network-on-Chip.

Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa

J. Circuits Syst. Comput., 2011

2010

A New Client Interface Architecture for the Modified Fat Tree (MFT) Network-on-Chip (NoC) Topology.

Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010

2008

A two-phase return-to-zero (RZ) asynchronous transceiver circuit for pipe-lined SoC interconnects.

Muhammad E. S. Elrabaa

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips.

Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2006

A High-Throughput Network-on-Chip Architecture for Systems-on-Chip Interconnect.

Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa

Proceedings of the International Symposium on System-on-Chip, 2006

An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications.

Muhammad E. S. Elrabaa

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2003

A new static differential CMOS logic with superior low power performance.

Muhammad E. S. Elrabaa

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2001

Split-Gate Logic circuits for multi-threshold technologies.

Muhammad E. S. Elrabaa, Mohamed I. Elmasry

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages.

Muhammad E. S. Elrabaa, Mohab H. Anis, Mohamed I. Elmasry

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1997

Low-power BiCMOS circuits for high-speed interchip communication.

Muhammad E. S. Elrabaa, Mohamed I. Elmasry, Duljit S. Malhi

IEEE J. Solid State Circuits, 1997

1994

Novel low-voltage low-power full-swing BiCMOS circuits.

Muhammad E. S. Elrabaa, Michael S. Obrecht, Mohamed I. Elmasry

IEEE J. Solid State Circuits, February, 1994