Muhammad Ali Shami

Orcid: 0000-0002-5598-249X

According to our database1, Muhammad Ali Shami authored at least 13 papers between 2009 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2019
Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays.
J. Signal Process. Syst., 2019

2017
Hardware Complexity Reduction in Universal Filtered Multicarrier Transmitter Implementation.
IEEE Access, 2017

Self-aware sensing and attention-based data collection in Multi-Processor System-on-Chips.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2016
A New Ultralightweight RFID Mutual Authentication Protocol: SASI Using Recursive Hash.
Int. J. Distributed Sens. Networks, 2016

2015
RCIA: A New Ultralightweight RFID Authentication Protocol Using Recursive Hash.
Int. J. Distributed Sens. Networks, 2015

2013
39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Classification of Massively Parallel Computer Architectures.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A Library Development Framework for a Coarse Grain Reconfigurable Architecture.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Address generation scheme for a coarse grain reconfigurable architecture.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Control Scheme for a CGRA.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

2009
Morphable DPU: Smart and efficient data path for signal processing applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009


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