Muhamed F. Mudawar

Orcid: 0000-0002-9593-3481

According to our database1, Muhamed F. Mudawar authored at least 7 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2024
Accelerating memory and I/O intensive HPC applications using hardware compression.
J. Parallel Distributed Comput., 2024

2023
Exact Versus Inexact Decimal Floating-Point Numbers and Arithmetic.
IEEE Access, 2023

2017
A Very Fast Trace-Driven Simulation Platform for Chip-Multiprocessors Architectural Explorations.
IEEE Trans. Parallel Distributed Syst., 2017

Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations.
ACM Trans. Archit. Code Optim., 2017

2006
A Locked Cache-based Synchronization Protocol for CMP.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications & Conference on Real-Time Computing Systems and Applications, 2006

2004
Scalable cache memory design for large-scale SMT architectures.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

One-Level Cache Memory Design for Scalable SMT Architectures.
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004


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