Mudit Bhargava

According to our database1, Mudit Bhargava authored at least 28 papers between 2008 and 2023.

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On csauthors.net:

Bibliography

2023
A survey of Digital Manufacturing Hardware and Software Trojans.
CoRR, 2023

2021
A Compact Model for Scalable MTJ Simulation.
CoRR, 2021

A Fokker-Planck Solver to Model MTJ Stochasticity.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling.
CoRR, 2020

2019
Secure hardware-entangled field programmable gate arrays.
J. Parallel Distributed Comput., 2019

A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Enhanced 3D Implementation of an Arm<sup>®</sup> Cortex<sup>®</sup>-A Microprocessor.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2015
A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement.
IACR Cryptol. ePrint Arch., 2015

Deeply hardware-entangled reconfigurable logic and interconnect.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

2014
Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques.
Proceedings of the Symposium on VLSI Circuits, 2014

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Reliable, Secure, Efficient Physical Unclonable Functions.
PhD thesis, 2013

Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states.
Proceedings of the 2013 IEEE International Test Conference, 2013

Stylometric Analysis for Authorship Attribution on Twitter.
Proceedings of the Big Data Analytics - Second International Conference, 2013

2012
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Side-channel Attack Resistant ROM-based AES S-Box.
Proceedings of the HOST 2010, 2010

Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses.
Proceedings of the HOST 2010, 2010

Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.
Proceedings of the 47th Design Automation Conference, 2010

2009
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.
Proceedings of the 27th International Conference on Computer Design, 2009

Low-overhead, digital offset compensated, SRAM sense amplifiers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008


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