Mu-Shan Lin
Orcid: 0000-0002-1268-1013
According to our database1,
Mu-Shan Lin
authored at least 7 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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On csauthors.net:
Bibliography
2024
A 0.296pJ/bit 17.9Tb/s/mm<sup>2</sup> Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2020
IEEE J. Solid State Circuits, 2020
2019
A 7nm 4GHz Arm<sup>®</sup>-core-based CoWoS<sup>®</sup> Chiplet Design for High Performance Computing.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2016
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
2014
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.
IEEE J. Solid State Circuits, 2014
2010
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010