Mu-Chi Chiang

According to our database, Mu-Chi Chiang authored at least 4 papers between 2014 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015

A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.

Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang

IEEE J. Solid State Circuits, 2015

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.

Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014