Mozammel H. A. Khan
Orcid: 0000-0002-8967-6095
According to our database1,
Mozammel H. A. Khan
authored at least 28 papers
between 2003 and 2024.
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Bibliography
2024
STICA: Spanning-Tree-Based Identification of Clusters With Agglomeration for Numerical Data.
IEEE Access, 2024
2018
VLSI Design, 2018
2017
Proceedings of the Reversible Computation - 9th International Conference, 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
2014
Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions.
IEEE Trans. Very Large Scale Integr. Syst., 2014
2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
2010
Multiple-Case Outlier Detection in Multiple Linear Regression Model Using Quantum-Inspired Evolutionary Algorithm.
J. Comput., 2010
Multiple-case outlier detection in least-squares regression model using Quantum-inspired Evolutionary Algorithm.
Int. J. Artif. Intell. Soft Comput., 2010
2009
Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits.
Proceedings of the ISMVL 2009, 2009
Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input.
Proceedings of the ISMVL 2009, 2009
2008
A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry.
J. Syst. Archit., 2008
Eng. Lett., 2008
Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
2007
J. Multiple Valued Log. Soft Comput., 2007
J. Syst. Archit., 2007
Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits.
Eng. Lett., 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
2006
J. Multiple Valued Log. Soft Comput., 2006
2005
Terary GFSOP Minimization Using Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades.
J. Multiple Valued Log. Soft Comput., 2005
2004
Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of generalized ternary gates.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004
2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003