Mozammel H. A. Khan

According to our database1, Mozammel H. A. Khan authored at least 27 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
First Steps in Creating Online Testable Reversible Sequential Circuits.
VLSI Design, 2018

2017
Automatic synthesis of quaternary quantum circuits.
J. Supercomput., 2017

Controlled and Uncontrolled SWAP Gates in Reversible Logic Synthesis.
Proceedings of the Reversible Computation - 9th International Conference, 2017

2016
Improved synthesis of reversible sequential circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Single-Electron Transistor Based Implementation of NOT, Feynman, and Toffoli Gates.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014
Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2011
Synthesis of Reversible Synchronous Counters.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010
Multiple-Case Outlier Detection in Multiple Linear Regression Model Using Quantum-Inspired Evolutionary Algorithm.
J. Comput., 2010

Multiple-case outlier detection in least-squares regression model using Quantum-inspired Evolutionary Algorithm.
Int. J. Artif. Intell. Soft Comput., 2010

2009
Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits.
Proceedings of the ISMVL 2009, 2009

Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input.
Proceedings of the ISMVL 2009, 2009

2008
A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry.
J. Syst. Archit., 2008

Synthesis of quaternary reversible/quantum comparators.
J. Syst. Archit., 2008

Design of Reversible/Quantum Ternary Comparator Circuits.
Eng. Lett., 2008

Cost Reduction in Nearest Neighbour Based Synthesis of Quantum Boolean Circuits.
Eng. Lett., 2008

Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2007
GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits.
J. Multiple Valued Log. Soft Comput., 2007

Quantum ternary parallel adder/subtractor with partially-look-ahead carry.
J. Syst. Archit., 2007

Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits.
Eng. Lett., 2007

Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

2006
On Universality of General Reversible Multiple-Valued Logic Gates.
J. Multiple Valued Log. Soft Comput., 2006

Design of Reversible/Quantum Ternary Multiplexer and Demultiplexer.
Eng. Lett., 2006

2005
Terary GFSOP Minimization Using Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades.
J. Multiple Valued Log. Soft Comput., 2005

2004
Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Genetic algorithm based synthesis of multi-output ternary functions using quantum cascade of generalized ternary gates.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2003
Multi-Output Galois Field Sum of Products Synthesis with New Quantum Cascades.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003


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