Mounir Meghelli
According to our database1,
Mounir Meghelli
authored at least 50 papers
between 1998 and 2024.
Collaborative distances:
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Bibliography
2024
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links.
IEEE J. Solid State Circuits, 2023
2022
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2020
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS".
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018
F5: Advanced optical communication: From devices, circuits, and architectures to algorithms.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the Second IEEE/ACM International Conference on Connected Health: Applications, 2017
2016
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.
IEEE J. Solid State Circuits, 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
IEEE J. Solid State Circuits, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012
2008
Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08).
IEEE J. Solid State Circuits, 2008
2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
2004
IEEE J. Solid State Circuits, 2004
2003
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems.
IEEE J. Solid State Circuits, 2003
IBM J. Res. Dev., 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems.
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
2000
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems.
IEEE J. Solid State Circuits, 2000
1998
IEEE J. Solid State Circuits, 1998
InP DHBT technology and design methodology for high-bit-rate optical communications circuits.
IEEE J. Solid State Circuits, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998